T bit confusion

[Alex_reynold]

Hi,
1.As it is mentioned in CM4 user guide and also explained in tutorial, 0th bit of PC is directly loaded to T bit.And CM4 supports only thumb state ISA.To execute/decode instructions in Thumb state 0th bit of PC should be 1 which means PC should always hold address with odd numbers (i.e ODD Locations).
2.But in the attached screenshot,

Top left corner - core register window,
top right side has disassembly window,
Bottom Left-expressions window

3.Actual queries are:
3.1 why PC is holding even address(PC:0x8000654 ). And in disassembly window, address of location from where instruction needs to be executed is also even and it is matching with value in PC which is correct(Current location :0x8000654).
3.2 Once control jumps into generate_interrupt() function[Defined at location 0x80005dc] LR should hold the return address of the function,i.e, location of the next line in main.c function =>printf line(line num in main.c file :148 and disassembly window:0x8000658). So after jumping into function LR should hold 0x8000658,But as shown in snapshot, it holds 0x8000659.
3.3 After bx lr instruction associated with genreate_interrupt() function value in LR should be copied back to PC right but here value as differed by 0x01 why?

[Tesla DeLorean]

The LR holds the ODD value as it indicates the type of code it's going to execute upon return.

In the Handlers it can contain magic values like 0xFFFFFFF9 or 0xFFFFFFFD as that is a call gate that unstacks context. Either MSP or PSP

[Pavel A.]

> why PC is holding even address

Because the T bit goes into the processor state bits. 

> So after jumping into function LR should hold 0x8000658,But as shown in snapshot, it holds 0x8000659.

Yes because LR holds not only the return address but also this bit from the status.

>  After bx lr instruction associated with genreate_interrupt() function value in LR should be copied back to PC right but here value as differed by 0x01 why?

And here we're again... LR bits 31..1 go into PC and bit 0 to the status. Please take your time to digest this ))

[Alex_reynold]

Could anyone please answer bit bit like section bus ection.I know I ahve asked many questions it that

[Alex_reynold]

Hi @KnarfB ,

Please look into this issue and help me to understand this better.

Best regards,

Alex

[KnarfB]

Well, everything was already said and nothing is broken.

In the famous "The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors" Joseph Yiu's writes about LR:

"Although the return address values in the Cortex-M processors are always even
(bit 0 is zero because the instructions must be aligned to half-word addresses), bit
0 of LR is readable and writeable. Some of the branch/call operations require that
bit zero of LR (or any register being used) be set to 1 to indicate Thumb state."

and, about PC:

"Since the instructions must be aligned to half-word or word addresses, the Least
Significant Bit (LSB) of the PC is zero. However, when using some of the branch/
memory read instructions to update the PC, you need to set the LSB of the new PC
value to 1 to indicate the Thumb state."

hth

KnarfB

[Tesla DeLorean]

The loading of PC is special cased to modify/check T bit. ie POP PC or BX LR

Loading of LR from PC also.

Perhaps this is covered in the TRM, ST's Programming Manual or Joseph Yiu's Essential Cortex-M3 texts to a level that suits your needs. 

[Alex_reynold]

Could you please share link for sts programming manual

[Tesla DeLorean]

https://www.st.com/resource/en/programming_manual/pm0214-stm32-cortexm4-mcus-and-mpus-programming-manual-stmicroelectronics.pdf

https://www.keil.com/dd/docs/datashts/arm/cortex_m3/r2p0/ddi0337g_cortex_m3_r2p0_trm.pdf

https://developer.arm.com/documentation/ddi0439/b/

https://wiki.ifsc.edu.br/mediawiki/images/2/29/MIPM3TUG.pdf

Not sure there's a Gate Level explanation of what's going on internally, or the slight-of-hand / special-casing of getting PSR.T in/out of PC/LR, ie the low order bit written to PC goes to the T-bit, and the high order bits get into the PC, with bit-0 appearing as zero. And loading LR (BLX), gets you the PC plus the T-bit.

If you clear PSR.T it's going to fault the processor as there's no support for 32-bit ARM code. In the ARM7TDMI the Thumb decode was more of a logical mapping to 32-bit forms the MCU would digest, ie more of an expansion from 16-bit to 32-bit opcodes. Whereas the Cortex-Mx's natively just decode the 16-bit Thumb2 forms.

[Alex_reynold]

DO you guys have link for Joseph Yiu book "The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors"