Posted on May 17, 2011 at 14:33Bit banging is generally used to describe a technique for emulating hardware protocols by driving GPIOs with appropriate levels at appropriate times. Sometimes timing is critical, like say for a serial UART type signal, and you'd need to use tight software timing loops to achieve appropriate bit timings. I2C is somewhat easier, as the clock doesn't have to be accurate or constant, the user gets to drive the bus as what ever speed is convenient, obviously within the 400 KHz, or whatever limit the peripheral has. Sync is often accomplished by holding off on the very last clock, ie for an RTC for example, wanting for the top-of-second before loading the timing registers internally by the RTC.
By a common GPIO bank, I mean say using PA.03, PA.05 and PA.07 (numbers plucked out of the air, no specific STM32 utilization considered). These all live on bank A, and you can modify them with a single write to a GPIO register. The pins will all transition at the external interface on the synchronous clock of the GPIO peripheral.
You'd define them as OD type GPIOs, perhaps 2MHz in terms of edges/drive/slew, and SDA1, SDA2, SCL respectively. You could use two SCL's but I wouldn't bother. Then you'd transition the pins in protocol sensitive manner (hold times, relative/temporal placement, etc), checking on ACKs, returned data, etc. If it just involves writing to the I2C slave, that would make things a tad simpler.
