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STM32U5 RAMCFG wait state config

Associate II


I'm currently using the STM32U575 to develop a product, and my clock configuration is set to the maximum of 160MHz because I'm dealing with a large amount of data. I have two SPI channels collecting data at a sampling rate of 20kHz, with each sampling returning 70 data points. During operation, I encounter Hardfaults on the bus, with bus fault information showing IBUSERR or PRECISERR. I suspect that the CPU and DMA are competing for the bus, causing errors. However, I found that by adjusting the wait state parameter in the RAMCFG configuration to 1 or 2, the system runs much more stably. Is RAM access unstable at 160MHz? Do you have any experience with configuring RAM wait states, or how to ensure reliable operation?

ST Employee

Dear @OneLine ,

you can refer to slide 8 here

if your configuration case is not inline , it is not normal and we never had such issue , you may check the race conditions from different masters writing on same memory . If possible to know if particular addresses are impacted ? To identify which RAM .

hope it helps ,