STM32N657xx Timer Clock(s)

[Robert Ritchey]

I am confused about which clock(s) drive the timers.  In the reference manual is says the APB clock drives the timers but there are 5 APB clocks.  Also, in STM32CubeMX there is a "Timer Group Clocks".  What clocks drive which timers or is the one drives all (Timer Group Clocks)? 

[TDK]

Go to the reference manual in the "Peripheral register boundary addresses" table and you can see which timer is within which APB.

The "timer group clock" is a separate clock you can use to clock individual timers. See timgx_ck below

It's also listed here which PCLK goes with which timer:

[Robert Ritchey]

I missed that in the "Peripheral register boundary addresses".  I guess I do not know what "PClkx" is and where it comes from.  I am using STM32CubeMX and am confused on how to set the clocks for the timers.  Nothing seems to match with the documentation.  What are the "Timer Clock Group" clocks.  

[TDK]

pclk1 is the APB1 clock here:

timer group clocks is this:

This is in the CubeMX clock tree which helps visualize it, but it should match the RM. What isn't matching the documentation?

[Robert Ritchey]

I see that.  I figured out that the PClk was the APBx clock after you told me what to look for.  What I don't understand is if either the PClk or "Timer Group Clocks" can be used for the timers and how to set them in STM32CubeMX.  In the RM is only mentions the APB clock.  On the timer diagram for each timer it show tim_pck for the simple timers and tim_pck and tim_ker_ck for the more advanced timers.  Nothing is mentioned about the multiple APB clocks or "Timer Group Clocks".  This is very confusing to me.  I am used to the smaller STM32 devices and I am trying to figure this out. 

[Robert Ritchey · Accepted solution]

I was told by the support team at ST that this is not true.  The "Timer Group Clocks" actually drive the timers.  

"Yes, the clocks are connected PCLK1 and PCLK2, as shown in the reference manual. I know the term "Timer Group clocks" is vague, but I think we can deduce what it does by looking at the definition of TIMPRE register field:

Bits 25:24 TIMPRE[1:0]: Timer clock prescaler selection
This bitfield is security-protected by a SEC signal from RIFSC, the SYSSEC bit, a PRIV
signal from RIFSC, or the SYSPRIV bit, and is publicly readable if SYSPUB = 1. It is set and
reset by software to control the clock frequency of all the timers connected to APB1 and
APB2 domains.
00: timg_ck = sys_bus_ck (default after reset)
01: timg_ck = sys_bus_ck / 2
10: timg_ck = sys_bus_ck / 4
11: timg_ck = sys_bus_ck / 8" 

Look at "Figure 45. Core and bus clock generation" for the divider and resultant timer clocks. 

[STOne-32]

Dear @Robert Ritchey ,

We got your question on our OnLine-Support support and will be back to you with a clarification, for follow-up an internal Number Ticket  #214797.

Regards,

STOne-32.