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STM32L4S5 Apparent discrepancy in maximum PLL clock


Hi There,

I'm trying to set the clock configuration of an STM32L4S5 and have spotted some ambiguities in the reference manual concerning the maximum input frequency to the PLL:

RM0432 6.4.4 says the following in the context of choosing the M value when programming the PLL:

The software has to set these bits correctly to ensure that the VCO input
frequency ranges from 2.66 MHz to 8 MHz

RM0432 6.2.5 says the following:

The PLLs input frequency must be between 4 and 16 MHz. The selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a clock frequency in the requested input range

DS12024 6.3.9 Gives a range of 2.66 - 16 MHz for FPLL_IN.

My configuration runs the MSI at 48 MHz, feeds this into the M divider for a 16 MHz output to the PLL, which provides an output of 80 MHz. Is this a valid configuration? Should I instead be increasing M to reduce the PLL input to 8 MHz?


Thanks in advance!





to be in the middle of the allowed range is probably best ; (2.66 MHz to 8 MHz );

so i would set prescaler to 6 MHz  for VCO input. (8 is also still ok.)

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