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STM32L496RGT6 Reducing core frequency while running same baud rate on CANBUS

Linas L
Senior II


In my project I need to get very low power usage device. It works with camera, so when I am taking picture I need maximum processor speed since I need to be at least 4x so DCMI could support full speed parallel data.

When I am done with my calculations, I could reduce speed to 1/8 or even more, since I just need to run CANBUS on 500Kbps

Problem is that frequency of core and nearly all system uses same clock domain, and if I reduce processor speed, I will reduce peripheral clock and thus, timing will be changed.

I have no idea when I get new CANBUS frame, so if I change this parameter and reconfigure CANBUS for lower speed operation with same 500kbps speed, I can lost some packet. And this is not acceptable.

What should I do in this situation ?

FDCAN is using LL_APB1_GRP1_PERIPH_CAN1 0693W00000KbWHDQA3.png 

Any ideas are welcome !

Principal III

Halting the core (WFI sleep mode) and continue on CAN RX IRQ is not an option?




Most peripherals have their clock mux to have independent clock source from the core. Otherwise, AHB and APB prescaler, as long as they have the same divide ratio could provide a partial answer. This thread is not new in this forum. Say your ahb abd apb are div 1 div8, core runs div1. Now in the same register, you may change to div8, div1. Peripherals remain same clock divider while core is div8.

Side effects to work around are wait states, dma on going transfer, interrupts, systick. I guess a core with dual clock setting registers would create a gear box which coulf even activate an interrupt boost when needed at low sw cost...