Hi Everyone.
Page 524, section 18.4.16 ADC timing of the STM32L476 Ref manual states.
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data resolution:
TCONV= TSMPL + TSAR = [ 2.5 |min + 12.5 |12bit ] x TADC_CLK
TCONV = TSMPL + TSAR = 31.25 ns |min + 156.25 ns |12bit = 187.5 ns (for FADC_CLK = 80 MHz)
This is almost exactly the same as, page 217 section, 11.5 Channel-wise programmable sampling time of the STM32F411 Ref manual.
The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time. The total conversion time is calculated as follows:
Tconv = Sampling time + 12 cycles
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
Tconv = 3 + 12 = 15 cycles = 0.5 μs with APB2 at 60 MHz
Heres my problem. When I set up and run the “ADC_RegularConversion_Interrupt�? example which is one of the many ADC examples in the CUBE library which runs the ADC in Continuous Conversion Mode, I get very close to the calculated Tconv time when run it on the STM32F411.
When I run seemingly the same code on the STM32L4, I can never get the calculated time, its always slower than the calculated, as if HCLK/SYSCLK is not correct.
As I’m trying to debug this issue I also ran the following code from one of the RCC examples that connects HCLK/SYSCLK to PA8:
/* Output SYSCLK on MCO1 pin(PA.08) */
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
On my DSO this shows it to be 80Mhz, and if I understand it correctly this is the clk that feeds APB2 where the ADC is located. What am I missing, is it some info in the RM I havnt read or understood?
Thanks
k.v
