Hi, Everyone
I am trying to setup STM32H7R7Z8 XSPI2 in Quad mode for APS6404L-3SQR QSPI PSRAM.
The original code is generated from MX v6.116.1 and developed with IDE v2.0.0.
HW info:
- The PSRAM is connected to XSPI2 with NCS, CLK, IO0~3. There is no DQS pin (PSRAM does not support it).
- The XSPI2 is setup in 133MHz frequency PSRAM supported.
- APS6404L-3SQR: 133MHz for 32 Bytes Wrapped Burst, 64Mb, 8M x 8bits, pagesize 1024 bytes,
SW configuration:
/* XSPI2 parameter configuration */
hxspi2.Instance = XSPI2;
hxspi2.Init.FifoThresholdByte = 4;
hxspi2.Init.MemoryMode = HAL_XSPI_SINGLE_MEM;
hxspi2.Init.MemoryType = HAL_XSPI_MEMTYPE_APMEM_16BITS;
hxspi2.Init.MemorySize = HAL_XSPI_SIZE_64MB;
hxspi2.Init.ChipSelectHighTimeCycle = 2;
hxspi2.Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE;
hxspi2.Init.ClockMode = HAL_XSPI_CLOCK_MODE_0;
hxspi2.Init.WrapSize = HAL_XSPI_WRAP_32_BYTES;
hxspi2.Init.ClockPrescaler = 0;
hxspi2.Init.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE;
hxspi2.Init.ChipSelectBoundary = HAL_XSPI_BONDARYOF_NONE;
hxspi2.Init.MaxTran = 0;
hxspi2.Init.Refresh = 0;
hxspi2.Init.MemorySelect = HAL_XSPI_CSSEL_NCS1;
if (HAL_XSPI_Init(&hxspi2) != HAL_OK)
{Error_Handler();}
sXspiManagerCfg.nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1;
sXspiManagerCfg.IOPort = HAL_XSPIM_IOPORT_2;
sXspiManagerCfg.Req2AckTime = 1;
if (HAL_XSPIM_Config(&hxspi2, &sXspiManagerCfg, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{Error_Handler();}
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/* memory manager: EXTMEMORY_1 */
extmem_list_config[0].MemType = EXTMEM_PSRAM;
extmem_list_config[0].Handle = (void*)&hxspi2;
extmem_list_config[0].ConfigType = EXTMEM_LINK_CONFIG_4LINES;
extmem_list_config[0].PsramObject.psram_public.MemorySize = HAL_XSPI_SIZE_64MB;
extmem_list_config[0].PsramObject.psram_public.FreqMax = 133 * 1000000u;
extmem_list_config[0].PsramObject.psram_public.NumberOfConfig = 0u;
/* Memory command configuration */
extmem_list_config[0].PsramObject.psram_public.ReadREG = 0u;
extmem_list_config[0].PsramObject.psram_public.WriteREG = 0u;
extmem_list_config[0].PsramObject.psram_public.ReadREGSize = 0u;
extmem_list_config[0].PsramObject.psram_public.REG_DummyCycle = 0u;
extmem_list_config[0].PsramObject.psram_public.Write_command = 0x38u;
extmem_list_config[0].PsramObject.psram_public.Write_DummyCycle = 0u;
extmem_list_config[0].PsramObject.psram_public.Read_command = 0xEBu;
extmem_list_config[0].PsramObject.psram_public.WrapRead_command = 0x00u;
extmem_list_config[0].PsramObject.psram_public.Read_DummyCycle = 6u;
EXTMEM_Init(EXTMEMORY_1, HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI2));When system startup, the SW can properly initializes the PSRAM with reset, toggle-burst-boundary(chip specific feature), readID and enabled to memory-mapped mode successfully. Below image shows the registers after init:
According to Errata: 2.4.1 Memory-mapped write error response when DQS output is disable
Description: If the DQSE control bit of the XSPI_WCCR register is cleared for memories without DQS pin, it results in an error response for every memory-mapped write request.
Workaround: When doing memory-mapped writes, set the DQSE bit of the XSPI_WCCR register, even for memories that have no DQS pin.
So I did "commandBase.DQSMode = HAL_XSPI_DQS_ENABLE" for memory-mapped write instruction.
Problem:
In memory-mapped mode, SW try to write 0x55 to RAM from start-address 0x70000000 and then read back for verification.
- The verification is success at beginning 24KB size - whatever the start-address is.
- After 24KB, the verification is failed time to time. And errors happen more if read run more time.
- The MCU hangup with free-run-read through whole PSRAM size.
It seems the XSPI has timing drift problem. Does anyone get the problem?
Question: Does XSPI support Quad mode for PSRAM without DQS pin?
1 ACCEPTED SOLUTION
Accepted Solutions
Hi Kaouthar, Thanks for your reply!
For HSLV, I checked the high-speed-option are disabled on both XSPI 1 and 2. See:
But the HSLV are enabled from MX->SBS. Shall I disable it too?
We will check the I/O/compensation from errata 2.2.15, and get back later.
Hi @KDJEM.1,
I did test according to errata 2.2.15. See below:
1) The error rate is significantly reduced by disabling automatic I/O compensation on XSPI pins (SW compensation is not applied), and slowdown the speed:
| XSPI-2 Clock (MHz) | Total Bytes | Error Bytes | Error Rate |
| 133 | 8MiB | 525740 ~ 685629 | 8.57% |
| 66.5 | 8MiB | 800 ~ 1000 | 120 PPM |
| 33.25 | 8MiB | 17 | 2 PPM |
2) Then apply SW I/O compensation on XSPI (Follow workaround from Errata 2.2.15)
The value of flash memory at address 0x08FFF840 @3.3 V is 0xFFFFFFFF. So we go with case-1: The calibration value from register SBS_CCVALR is 8. The result shows the SW compensation does not help in high speed, and a little bad with low speed:
| XSPI-2 Clock (MHz) | Total Bytes | Error Bytes | Error Rate |
| 133 | 8MiB | 527700 ~ 685694 | 8.57% |
| 66.5 | 8MiB | 800 ~ 1191 | 200 PPM |
| 33.25 | 8MiB | 13 ~ 30 | 4 PPM |
Double check the SBS registers:
Summary:
- The DQSE bit of the XSPI_WCCR register is set for doing memory-mapped writes.
- Both XSPI1_HSLV and XSPI2_HSLV are disabled.
- Automatic I/O compensation is disabled in XSPI1 and XSPI2, with or without SW compensation applied.
All these can't fix the unstable problem. Any suggest?
By testing with lower speed, we find there may be EMC issue on board.
Thanks!
Leo Ruan
Hi @KDJEM.1
The VDD for MCU and PSRAM is 3.3v. It is confirmed that I/O HSLV is not set on my board.
To avoid the damage case, I checked the HSLV and do all tests on 3 boards. Get same result.
I did not check the pin-mux settings since this is generated by MX.
Thanks!
Leo Ruan
