STM32H753 QUADSPI – Clarification on Dual Bank, IO Lines, and Multi-Flash Possibilities

[jyothzz]

Hi Team,

I am designing a custom PCB using STM32H753 and planning to use the QUADSPI peripheral for external memory. My use case is data read/write (indirect mode) — not XIP or memory-mapped execution.

While working in STM32CubeMX, I came across some configurations that are confusing, and I’d like to clarify the actual hardware behavior.

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1. Dual Bank vs Chip Select behavior

In CubeMX, I can configure:

• QuadSPI Mode: Dual Bank with Quad Lines

• Chip Select options:

  • Enable Chip Select 1 for both banks

  • Enable Chip Select 2 for both banks

  • Enable Chip Select for each bank

My understanding:

• NCS → Bank1

• NCS2 → Bank2

Questions:

• If I select “Enable Chip Select 1 for both banks”, does this mean:

  • Only one physical flash is used and banks are logical partitions?

  • Or is there any way two physical memories are still utilized?

• What is the exact meaning of “bank” in this context (hardware vs logical)?

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2. BK1_IOx and BK2_IOx pins confusion

CubeMX exposes:

• QUADSPI_BK1_IO0–IO3

• QUADSPI_BK2_IO0–IO3

This gives the impression of 8 data lines (4 per bank).

Questions:

• Are BK1_IOx and BK2_IOx:

  • Independent data buses for each bank?

  • Or alternate pin mappings of the same internal IO signals?

• If both sets are enabled simultaneously (as CubeMX allows), are these pins internally shorted?

• What is the correct way to route these signals on PCB when using:

  • Single flash

  • Dual flash (2-chip setup)

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3. Multi-flash usage beyond 2 chips

Given the hardware has:

• 1 shared IO bus

• 2 chip select lines (NCS, NCS2)

Questions:

• Is it possible in any supported way to interface 4 QSPI flash chips

4. Manual Chip Select using GPIO

Questions:

• Can we use GPIO-controlled chip select instead of the hardware NCS/NCS2 pins in QUADSPI?

• Or is hardware-controlled CS mandatory for correct operation?

• If GPIO CS is used:

  • Will timing or protocol issues occur?

  • Is it reliable for read/write (non-memory-mapped mode)?

5. Dual Bank + 1 CS behavior

Questions:

• In dual bank with single CS configuration, is it possible to:

  • Read/write data to two different physical chips?

  • Or does it always operate on only one physical chip?

• If it is only one chip, is this configuration purely a logical memory split?

6 Extending dual-bank concept

Questions:

• If dual bank works with 2 CS lines (2 chips), is there any way to extend this concept to:

  • 4 chips (e.g., 2 banks × 2 chips each)?

• Can STM32 QUADSPI handle such a setup in any supported or semi-supported way?

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7. Summary of my understanding (please correct if wrong)

• QUADSPI has only one internal 4-bit data bus

• BK1_IOx and BK2_IOx are not independent buses

• True multi-chip support is limited to 2 devices via NCS/NCS2

• “Dual bank with single CS” is logical partitioning, not physical dual memory

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I would really appreciate clarification from someone who has worked with this peripheral at hardware level or designed boards using it.

Thanks in advance!

JYOTHISH B CHANDRAN

[mƎALLEm · Accepted solution]

Hello @jyothzz and welcome to the ST community,

I think the answer to you question has been answered in the AN4760 "Introduction to Quad-SPI interface for STM32 MCUs and MPUs" / Table 9. Dual-Flash hardware configurations: