2024-08-16 12:56 AM
Hello,
while using this mcu 16bit adc a strange thing happens.
the adc signal is test under a sinusoid signal(0.5Hz from a signal generator), and as shown in the figure at certain level adc keeps unchanged, after leaving this level then the signal increased again, however the trace has deviate from a standard sin signal.
as I checked the value is 0d57345 which is 0b1101 1111 1111 1111 and this phenomenen occurs everytime the 14th bits is 0 and lower bits are 1.(at 0b0001 1111 1111 1111, 0b0101 1111 1111 1111, 0b1001 1111 1111 1111 a value constant platform occurs)
and at some other points there is a leap where the trace goes back to original trace.
this happens for 14bits resolution adc sometimes as well.
sometimes for 15th bit as well.
I have tried several times to fix this including
1.longer sampling cycs
2.longer delay between conversion
3.independent mode/ dual mode(adc1, adc2)
4.LL LIB/HAL LIB
5.fast/slow adc clock
6.calibration/no calibration before enable and start conversion
7.fast/slow channel
none of above worked, so anyone have any idea please kindly reply
thanks
IOC file has been attached and my cube version is 6.12.0-RC9
2024-08-16 06:08 AM
Generally, this is caused by a poorly decoupled VDDA or VREF+ supply. Can you share your schematic/layout?
2024-08-17 10:42 PM
Dear @mize ,
if possible to share your hardware schematics : the exact MCU part number and package ,decoupling and which channels used . Here is an App Note on this 16-bits ADC and its performance. The input signal is also key to be very clean from a low noise source - using a standard lab generator and wires hooks at 16-bits should be carefully designed.
Hope it helps ,
STOne-32
2024-08-18 07:37 PM
Hi, this is my schematic diffierential signal pair from sensor amplified by ina8211dr then directly feed to MCU ADC channel.
There is one problem that I have disscussed with my hardware colleague that the capacitor between VDDA/GND and Vref+/GND is different with the AN2834 recommanded schematic that bypass capacitor with 1uf//1nf 1uf//100uf, but he says it won't affect too much, I'm not so sure about this for I mainly doing software, what's your opinion?
2024-08-18 07:50 PM
and Vref+ is indenpent with VDDA
2024-08-18 08:06 PM
Hi,
I have shared my relevant schematics in other replies, please refer to it. I tried two source, one was from designed sensor and amplified and one was directed from a signal generator device. So it is mostly a MCU problem, the chip I'm using is STM32H750VBT6 V 7837C VQ PHL 78 335 with QFP100 package, the VDDA and Vref+ are independently from different LDO and at different level.
I have tried fast channel 4,5 slow channel 7,8, and another MCU for I have 2 sample.
And as I have mentioned in other reply: There is one problem that I have disscussed with my hardware colleague that the capacitor between VDDA/GND and Vref+/GND is different with the AN2834 recommanded schematic that bypass capacitor with 1uf//1nf 1uf//100uf, but he says it won't affect too much.
So if you have any further idea please kindly comments, thanks a lot!
2024-08-19 06:39 AM
How are A_3.3V and ADVREF being generated?
A 1 uF cap can help things. Since you are seeing issues, and this issue can be cause by improper decoupling caps, I would suggest fixing that in hardware to see if it makes a difference. It is the most logical thing to check first.
GND and AGND should be tied directly, or (perhaps better) not be separate at all. Presumably they are, but not that 0 Ohm jumper resistor are not really 0 ohms.
Everything else seems okay. I'm assuming there are decoupling caps on each power pin, but that's not likely to be the cause here even if it's not true.
2024-08-19 09:44 AM
From my experience with nucleo-H743zi2 board (stm32H743zi2) - all decoupling capacitors circuits designed by ST, and board manufactured by ST, ADC bits 12-13-14-15 are just noise. Doesn't matter how low source impedance of the inputs driver or what reference voltage is. IC package could be a cause.
The only way to get 16-bits is using oversampling, running adc as fast as possible.
BTW, ad821 is powered by 5V may presents risk of damaging IC, consider 3.3V powered buffer for that. LM358 for reference is also wrong choice, OPA has not sufficient GBW to drive switching capacitive load. In both sides - reference inputs and signal inputs good capacitance required to null out charge kickback interference. Look on google for correct SAR adc interfacing.
2024-08-20 12:22 AM
HI TDK,
I tired fix the 1uf cap today but not work.
power supply are generated from LDOs, which is adaptor 12v-> LM1117MPX 5v -> TPS73633DBVR 3.3v -> TL431AIDBZR ADVREF. AGND/GND are tighted through a 0ohm, perhaps I should remove it. But it seems not where problem lies.
guess I need to give up internal adc, thx any way.