2025-12-16 8:00 AM - last edited on 2025-12-16 8:13 AM by Andrew Neil
Hi in an dual core stm32h7, if we use each iwdg for each cores, when iwdg trigger reset,it will reset the particular core or both the cores will reset.
If particular core reset happens means, how to manage the other core from initial boot.
Suppose if cm7 IWDG trigger reset, meanwhile cm4 is running on other side, during this time after cm7 reset we have to read the iwdg register, then perform nvic reset?
If cm4 iwdg trigger reset, it will affect the other side running cm7 core.
Regards,
Srinath
2025-12-16 8:18 AM
They pull NRST low which will reset both cores.
2025-12-16 8:39 AM
2025-12-16 8:53 AM - edited 2025-12-16 8:58 AM
Hello,
From RM0399:
2025-12-16 9:24 AM
Correct. All reset sources are routed to NRST which resets the entire chip. Literally the same effect as holding the reset button down.