Hi ST team,
I am seeing what appears to be a silicon-level issue on STM32H563RGV6, revision X, related to the SWAP_BANK option byte.
When SWAP_BANK is enabled, a USB OUT endpoint stops being re-armed during a flash mass erase of the inactive bank. The USB ISR still executes, but the BULK OUT path wedges because the OUT endpoint is no longer re-armed. Once the mass erase completes, the endpoint behavior returns to normal.
Key observations:
MCU: STM32H563RGV6
Revision: X
The issue is specifically tied to SWAP_BANK being set
The problem occurs during mass erase of the inactive bank
The symptom is specifically USB OUT not being re-armed
This does not look like a total USB interrupt loss; ISR activity can still occur
Other endpoint activity is not affected in the same way
The entire application, including vector table and read-only data used by the relevant path, is relocated to SRAM
Bank selection / inactive-bank arithmetic has been verified and is correct
This does not appear to be a normal software issue. The behavior tracks the SWAP_BANK address remap condition.
My current suspicion is that because SWAP_BANK changes flash address mapping, it may have downstream effects somewhere in the internal address decode / bus matrix / flash-peripheral interaction path during mass erase, and that this is causing the USB OUT endpoint state/update path to fail to reach the condition required for re-arm.
The issue I would like ST to investigate is:
On STM32H563RGV6 revision X, when SWAP_BANK is enabled, a mass erase of the inactive flash bank can cause a USB OUT endpoint to stop being re-armed, even though the system is running entirely from SRAM and inactive-bank selection is correct.
I recognize this is a rare corner case, since many designs would normally pause USB traffic during a flash mass erase. Still, the behavior appears deterministic on STM32H563RGV6 revision X when SWAP_BANK is enabled, so I wanted to report this in case it points to an uncharacterized hardware interaction involving the bank remap.
If useful, I can provide a minimal repro focused specifically on:
STM32H563RGV6 rev X
SWAP_BANK enabled
code / vector table / relevant read-only data all in SRAM
mass erase on inactive bank
active USB OUT traffic during erase
OUT endpoint stops being re-armed until erase completion
Has ST seen this before, or can this be reproduced internally?
Thank you.
