STM32G474 LSE oscillator not ready ?

[Manu Abraham]

Hi Folks,

Greetings !

With a Nucleo-G474RE MB1367C, with an onboard 32.768kHz crystal:

I am trying to turn ON the LSE oscillator, but the LSE oscillator does not get RDY at all.

This is what I tried to do:

void SystemClock_Config(void)
{
	LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
 
#if 0
	/* Enable boost mode to be able to reach 170MHz */
	LL_PWR_EnableRange1BoostMode();
#endif
 
	LL_RCC_HSI_Enable();
	while (LL_RCC_HSI_IsReady() != 1) {};
 
	LL_RCC_HSE_Enable();
	while (LL_RCC_HSE_IsReady() != 1) {};
 
#if 0
	LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMHIGH);
	LL_RCC_LSE_Enable();
//	LL_RCC_LSE_EnableCSS();
	while (LL_RCC_LSE_IsReady() != 1) {};
#endif
 
	/* Main PLL configuration and activation */
	LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_6, 85, LL_RCC_PLLR_DIV_2);
 
	LL_RCC_PLL_Enable();
	LL_RCC_PLL_EnableDomain_SYS();
	while (LL_RCC_PLL_IsReady() != 1) {};
 
	/* Sysclk activation on the main PLL */
	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {};
 
	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
 
	/* Insure 1µs transition state at intermediate medium speed clock based on DWT */
	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
	DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
	while (DWT->CYCCNT < 100);
 
	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
	LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
 
	LL_Init1msTick(170000000);
	LL_SetSystemCoreClock(170000000);
	LL_RCC_SetUSARTClockSource(LL_RCC_USART2_CLKSOURCE_PCLK1);
}

Any thoughts, what I am missing ?

Thanks,

Manu

[Uwe Bonnes]

In your example, enabling LSE is commented out, so it never happens. LSE getting stable so that LSE_READY gets set can take considerable time. Enable is early, do the rest of the initialization beside things requireing LSE , wait for LSE and do the rest.

[Manu Abraham]

Hi Uwe,

I've commented it out to make sure that the rest of the code runs.

In the test case that I am able to successfully run, it does not have the #if 0.

The #if 0 was put in to avoid the indefinite loop with "while (LL_RCC_LSE_IsReady() != 1) {};"

Just to make doubly sure that the it is looping for "LSE_IsReady".

Any other thing that comes to your mind ?

Thanks,

Manu

[Manu Abraham]

I can say for sure, however long I wait, LSE_RDY does not happen.

Verified the same, with this:

void SystemClock_Config(void)
{
	LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
 
	LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_MEDIUMHIGH);
	LL_mDelay(1000);
	LL_RCC_LSE_Enable();
	LL_mDelay(1000);
 
	LL_RCC_HSI_Enable();
	while (LL_RCC_HSI_IsReady() != 1) {};
 
	LL_RCC_HSE_Enable();
	while (LL_RCC_HSE_IsReady() != 1) {};
 
	LL_mDelay(1000);
 
 
	/* Main PLL configuration and activation */
	LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_6, 85, LL_RCC_PLLR_DIV_2);
 
	LL_RCC_PLL_Enable();
	LL_RCC_PLL_EnableDomain_SYS();
	while (LL_RCC_PLL_IsReady() != 1) {};
 
	/* Sysclk activation on the main PLL */
	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {};
 
	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
 
	/* Insure 1µs transition state at intermediate medium speed clock based on DWT */
	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
	DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
	while (DWT->CYCCNT < 100);
 
	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
	LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
 
	LL_Init1msTick(170000000);
	LL_SetSystemCoreClock(170000000);
	LL_RCC_SetUSARTClockSource(LL_RCC_USART2_CLKSOURCE_PCLK1);
 
	// LSE RDY does not occur!
	while (LL_RCC_LSE_IsReady() != 1) {};
}

Thanks,

Manu

[Manu Abraham]

Finally, solved the problem!

Just before doing a LSE enable, enabling backup access, with a forced backup domain reset/release did solve the problem.

Just for completion sake ..

Cheers,

Manu