STM32G473VET3 SPI master NSS

[HoangDu]

Hi ST teams,

I use STM32G473VET3 on my design. On the datasheet, SPI4 had 3 NSS pins hardware: PE3, PE4 and PE11.

If I use other GPIO excluding for the NSS pin function, there are any potential issue?
Ex: SPI bus can not work at maximum speed.

On my design, I use SPI4 is master and PF2, PF9, PE3, PE4, PE5 for slave chip select function.

Thanks.

[TDK]

If you're controlling the CS/NSS pins manually (GPIO output and toggle), there are no downsides to choosing a different pin. It won't affect max clock rate.

If you have multiple slaves, you have no choice but to control CS/NSS manually.

[HoangDu]

Thank you for reply.

So i understand that there are no issue/limited when control CS/NSS manually instead use "automatic" CS/NSS control?