2025-04-07 3:02 PM
Hi ,
I am using STM32G4 to receive USART data from external interface and USART buffer overrun when USART interrupt conflicts with Flash Erase operation.
As mentioned in STM32G4 Reference manual , in single bank mode, any read operation while writing/erasing flash
stalls the bus until current flash operation is complete. To mitigate this performed following,
After all these changes , USART buffer still overruns when it conflicts with Flash erase operation
Request you to share your views.
Regards,
Hareesha
Solved! Go to Solution.
2025-04-15 12:02 PM
Hi All,
Thanks for the response . Issue is resolved now.
Refer application notes section 2.2 to execute ISR handler from CCM SRAM.
Regards,
Hareesha
2025-04-07 4:11 PM
So there must be some command to have the STM32G4 to erase the flash. Do you not return and ack to let the external device start sending packets of data?
2025-04-08 9:05 AM
Hi ,
Thanks for the reply, Flash erase and write sequence works fine. However issue happens when Flash erase conflicts with USART data dequeuing. USART data reception is interrupt driven , data deque happens at UART ISR handler.
My understanding is Flash erase is interruptible.
Regards,
Hareesha
2025-04-08 9:21 AM
Have you changed the interrupt priorities in the NVIC?
2025-04-08 9:30 AM
Why interrupt priority is required??. I don't use flash interrupt. I use only USART interrupt.
2025-04-08 10:01 AM
Also one more question, Can context switch happens when flash erase in progress?? CPU uses AHB bus to perform Context switching.
2025-04-08 1:21 PM
Attach some code for the UART Callback and describe what you're doing to start the flash erase and the UART communication. And how much data are you receiving?
As @Methew mentioned, use the DMA in circular mode.
2025-04-15 12:02 PM
Hi All,
Thanks for the response . Issue is resolved now.
Refer application notes section 2.2 to execute ISR handler from CCM SRAM.
Regards,
Hareesha