STM32G4: USART buffer overrun during Flash Erase operation

[harisuvarna]

Hi ,

I am using STM32G4 to receive USART data from external interface and USART buffer overrun when USART interrupt conflicts with Flash Erase operation. 

As mentioned in STM32G4 Reference manual , in single bank mode, any read operation while writing/erasing flash 

stalls the bus until current flash operation is complete. To mitigate this performed following,

• Moved ISR handler and subroutines invoked inside ISR to SRAM
• Moved Interrupt Vector table to SRAM     

After all these changes , USART buffer still overruns when it conflicts with Flash erase operation

Request you to share your views.

Regards,

Hareesha

[Karl Yamashita]

So there must be some command to have the STM32G4 to erase the flash. Do you not return and ack to let the external device start sending packets of data?

[harisuvarna]

Hi ,

Thanks for the reply, Flash erase and write sequence works fine.  However  issue happens when Flash erase conflicts with USART data dequeuing. USART data reception is interrupt driven , data deque happens at UART ISR handler.

My understanding is Flash erase is interruptible. 

Regards,

Hareesha

[Karl Yamashita]

Have you changed the interrupt priorities in the NVIC?

[harisuvarna]

Why interrupt priority is required??. I don't use flash interrupt. I use only USART interrupt.

[harisuvarna]

Also one more question, Can context switch happens when flash erase in progress?? CPU uses  AHB bus to perform Context switching.

[Karl Yamashita]

Attach some code for the UART Callback and describe what you're doing to start the flash erase and the UART communication. And how much data are you receiving?

As @Methew mentioned, use the DMA in circular mode.

[harisuvarna · Accepted solution]

Hi All,

Thanks for the response . Issue is resolved now.

• Moved, Interrupt table , all  ISR handler and associated functions into CCM SRAM memory location.
• Moved functions invoked after flash erase start to CCM SRAM memory location.

Refer application notes section 2.2 to execute ISR handler from CCM SRAM.

https://www.st.com/resource/en/application_note/an4296-use-stm32f3stm32g4-ccm-sram-with-iar-embedded-workbench-keil-mdkarm-stmicroelectronics-stm32cubeide-and-other-gnubased-toolchains-stmicroelectronics.pdf

Regards,

Hareesha