STM32G4 TIM3_ARR and TIM4_ARR width

[StevenR]

I believe there is an error in the STM32G4 Series Reference Manual regarding the width of TIMx_ARR for timers 3 and 4.

The reference manual shows a width of 20 bits for TIMx_ARR for timers 3 and 4, below.

However, both TIM3 and TIM4 are 16-bit timers, as shown below.

The following experiment on STM32G4 hardware aligns with the 16-bit understanding. 

1. Write pattern 0x12345678 to TIM3_ARR.
2. Read TIM3_ARR, result is 0x00005678. Result should be 0x00045678 if width was 20 bits.

On STM32G4 series, for timers 3 and 4, is the width of TIMx_ARR 16 bits or 20 bits? 

[Michal Dudka · Accepted solution]

It is up to you. 16bits in "non dithering" mode. Additional 4 bits is used in Dithering mode.

[StevenR]

Thank you for the clarification.