STM32F746 Startup-Problem with DCache - AN4667

michael2399 · ‎2016-12-16

Posted on December 16, 2016 at 11:08

Hello,

I have problems with a STM32F746 and DCache. Without DCache my software runs perfectly. If I enable the DCache (first invalidate it and the Enable), then I can't start the board.

I have check my source code, the document (Programmer Manual from STM32, the AN4839 [L1-Cache on STM32F7], the errata of Cortex M7 and STM32F746, but I have no idea.

After a power on, the processor runs in a hard fault. The IMPRECISERR in System Control - Bus Fault Status register and the AXIM-Bit in ABFSR (Auxiliary Bus Fault Status register) are set. The AXIM Type is 2.

If I understand this bits right then someone write (due to the IMPRECISERR) on wrong address via the AXIM-Bus. The AXIM-Slaves are the FLASH, SRAM, FMC and QUAD-SPI. I don't use FMC and Quad-SPI. FLASH is read only - therefor I suggest the problem is according to the SRAM. This can match to a problem with the DCache. (Incorrect invalidate?)

In the AN4667 (STM32F7 Series system architecture and performance) I found one sentence which I don't understand: Page 43 - last sentence (Chapter 4.2 Tips, last sentence).

'It is not recommended to enable the cache before calling the main function, that is, before the scatter load phase, because a hard fault may occur'.

What means this? Why a hard fault does occur? Is this a reason for my problem?

Best regards, Michael

#ada #stm32f7 #startup #dcache

Amel NASRI · ‎2016-12-16

Posted on December 16, 2016 at 13:24

Hi @ada_fan,

In the AN4667 (STM32F7 Series system architecture and performance) I found one sentence which I don't understand: Page 43 - last sentence (Chapter 4.2 Tips, last sentence).

'It is not recommended to enable the cache before calling the main function, that is, before the scatter load phase, because a hard fault may occur'.

This means that you shouldn't enable the cache in startup file or in the system_init.c file.

To farther investigate your issue, could you please provide the following details:

which RAM are you using?
Are you enabling MPU? If yes, which configuration you made for MPU?
what is your IDE?

Thanks.

-Amel-

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

michael2399 · ‎2016-12-16

Posted on December 16, 2016 at 13:52

I use the SRAM1 and SRAM2. Yes I have enable the MPU. I have only a MPU-configuration for SRAM2. SRAM2 is configured as not cachabel. I use the SRAM2 for Ethernet and SPI which both use DMA-Transfers.

Our software is written in Ada (see

http://www.adacore.com

The programming studio is GPS. We use winIDEA to debug our software.

Ada is a language for mission-critical software.

waclawek.jan · ‎2016-12-16

Posted on December 16, 2016 at 13:38

This means that you shouldn't enable the cache in startup file or in the system_init.c file.

Yes, but why?

JW

STM32 hobbyist · ‎2016-12-16

Posted on December 16, 2016 at 14:46

Could you configure the SRAM1 MPU attributesin Write-Through? as following:

Note: do not forget to change MPU_InitStruct.Number value as you already used the MPU for SRAM2

MPU_Region_InitTypeDef MPU_InitStruct;
 
 /* Disable the MPU */
 HAL_MPU_Disable();
 /* Configure the MPU attributes as Write Through for SRAM1 just only the first 128kB */
 MPU_InitStruct.Enable = MPU_REGION_ENABLE;
 MPU_InitStruct.BaseAddress = 0x20010000;
 MPU_InitStruct.Size = MPU_REGION_SIZE_128KB;
 MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
 MPU_InitStruct.Number = MPU_REGION_NUMBER0; /* Please change this number as you already used MPU for SRAM2 */
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
 MPU_InitStruct.SubRegionDisable = 0x00;
 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
 HAL_MPU_ConfigRegion(&MPU_InitStruct);
 
 /* Enable the MPU */
 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?

STM32 hobbyist · ‎2016-12-16

Posted on December 16, 2016 at 14:18

Because at this stage (scatter loading), the data (stack and ZI data) are not yet intilized, enabling cache during this period may introduce data corruption due to data incoherency between the content of the cache and the memory. This induce a hard fault!

Enabling cache before the main does not have any added value. It's recommended to enable it after entering main function.

STM32

waclawek.jan · ‎2016-12-16

Posted on December 16, 2016 at 15:05

Thanks.

What is 'scatter loading' And what is 'ZI data'?

JW

waclawek.jan · ‎2016-12-16

Posted on December 16, 2016 at 15:19

Waclawek.Jan wrote:

Thanks.

What is 'scatter loading' And what is 'ZI data'?

JW

Okay I found

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0474k/pge1362065973150.html

- so this is ARM/Keil parlance for initialization of static/global variables which happens during startup.

But if

invalidate

then enable the cache, how could that be incoherent then, at whatever moment after reset?

JW

michael2399 · ‎2016-12-20

Posted on December 20, 2016 at 09:43

Good Morning,

sorry for my late answer. I procure a nucleo board with stm32f7 I create a simple project with STM32CubeMX. There I have a similar problem. Maybe it is not a problem with the cache but with the MPU.

Here is my init for SRAM2:

 MPU_InitStruct.Enable = MPU_REGION_ENABLE;  MPU_InitStruct.Number = MPU_REGION_NUMBER1;  MPU_InitStruct.BaseAddress = 0x2004C000;  MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;  MPU_InitStruct.SubRegionDisable = 0x0;  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;   HAL_MPU_ConfigRegion(&MPU_InitStruct);    /* Enables the MPU */  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?

Which TEX-Level is right? I attach my project. If the mpu enable, then I get a trap (default handler).

Best regards, Michael

________________

Attachments :

CacheTest.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hyli&d=%2Fa%2F0X0000000bFa%2FsL6tlW6jRJ504sokp98yAG_u6WkEG1KxAzGkj.hXf6U&asPdf=false

STM32 hobbyist · ‎2016-12-20

Posted on December 20, 2016 at 15:52

Hello

Michael;

Did you already test your application without configuring the MPU for SRAM2? if yes, did the problem disappear?

Did you tried TEX LEVEL 0 for SRAM2?

if yes, di

d

the problem disappear?

Also in your stm32f7xx_it.cfile, only systick handler was declared that's why your application goes to

default handler. So It can be a hardfault. Please add the definition of HardFault_Handler() in stm32f7xx_it.cfile as following:

void HardFault_Handler(void)

{

/* Go to infinite loop when Hard Fault exception occurs */

while (1)

{

}