STM32F723x USB HS CoreReset Issue

[BRapo.1]

Hello, for the last couple of days I've been trying to set up my STM32F723ZET6 project as a USB HS CDC device with internal PHY.

My code gets stuck in this loop

  do
  {
    count++;

    if (count > HAL_USB_TIMEOUT)
    {
      return HAL_TIMEOUT;
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);

inside the function .staticHAL_StatusTypeDefUSB_CoreReset(USB_OTG_GlobalTypeDef *USBx) in the file stm32f7xx_ll_usb.c

I've been reading and it seems like a common issue. I've tried applying some solution that work for other people, although they were asking for other models of STM, Without success.

For what I read it seems to be some kind of timing or clock problem. I have no experience with USB and I don't really know much about how CUBEMX implementation works.

What I tried:

- Adding a 50ms delay before this loop

- Adding __HAL_RCC_SYSCFG_CLK_ENABLE(); to my HAL_MspInit function (Actually CUBEMX already did that)

-Adding __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); to my HAL_MspInit function

- I also added both enables to the main.c file before MX_USB_DEVICE_Init(); just for trying

Some additional information:
I'll put some pictures here of various configuration and some info I think might be relevant:
Clock configuration:

Every other Mux not shown in the picture is greyed out

USB_OTG_HS config

USB_Device Config

Power management:
One of the things chatGPT suggested was about the VBUS detection. It says that it must be enabled (it may be talking about other STM32 model). I didn't find any PWR configuration in my pinout view, not under System Core neither in the categories list. I don't know if my version of STM manages that internally.

-VDD12OTGHS pin is bypassed with a 2.2uF ceramic capacitor
-OTG_HS_REXT pin is pulled down with a 3K 1% resistor
-Both VDDUSB and VDDSDMC are managed by an external TPS389033 power management IC to generate a small delay after powering VDD, as specified by the datasheet. (I also tried bypassing it). And both are bypassed with a 100nF and a 10uF ceramic capacitor.

Please ask if you need any extra information.
Thank you!

[waclawek.jan]

Read out and check content of all registers related to the PHY's supply and clock. Measure voltage on VDD12OTGHS pin. Make sure RCC_APB2ENR.OTGPHYCEN is enabled as well as RCC_AHB1ENR.OTGHSEN , and that USBPHYC_PLL1 is set properly. Also make sure HSE is working as intended, perhaps outputting it to MCO.

> chatGPT

Maybe you should prefer reading the datasheet and RM.

JW

[FBL]

Hi @BRapo.1 

Do you use reference board F723E-Disco? Or custom board? I suggest check compiler optimization, PHY frequency. Try to decrease CPU frequency. 

[BRapo.1]

Thanks for your reply, I checked the registers and RCC_APB2ENR.OTGPHYCEN and RCC_AHB1ENR.OTGHSEN are both enabled.
I checked the value of USBPHYC_PLL1, it is enabled and set to 16Mhz (I don't really know what those 16Mhz mean)
I also checked USBPHYC_LDO and USBPHYC_LDO.LDO_DISABLE is set to 1, I don't know if the LDO should be enabled at the point of the core reset.

I measured the voltage at the VDD12OTGHS pin and it's 1.25V

I did a Master Clock output and got a frequency reading of 16Mhz

[FBL]

Hi @BRapo.1 

The RCC OTGHSULPIEN is still required even for the internal HS PHY. We have ongoing internal tickets 204861 204937 to update code generation to align with the firmware. 

[BRapo.1 · Accepted solution]

This was exactly the solution, In addition I must also add the enable of the OTGHSEN.

I added this three lines in my main() and it worked. The delay might not be needed

  /* USER CODE BEGIN SysInit */
    RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSEN;        // enable USB OTG HS clock
    RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSULPIEN;   // enable ULPI clock

    HAL_Delay(50);
  /* USER CODE END SysInit */

Thank you