LSERDY is set when LSE oscillations are detected, but cleared only when LSE is switched off (by clearing LSEON ). And, given the description in RM (After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.) I am not sure it LSERDY will be cleared at all if the oscillator is not working when LSEON is cleared, so it may require backup-domain reset to be cleared in that case.
In other words, LSERDY is not the best indicator LSE is running. For that purpose you may want to compare LSE to other clock, e.g. using the LSE->TIM5 interconnection (see TIM5_OR).
Some newer STM32 families have CSS on LSE (LSECSS, see e.g. 'L4), but 'F4 don't.
JW
