STM32f439 PCB Design Consideration

[mrniknejad]

Posted on November 14, 2014 at 15:15

Hi 

I'm new in High frequency PCB design and i want to make my own STM32F439 board , so my question is : should i have any consideration in my design for signal integrity problems when maximum clock is 180 Mhz and tracks on pcb have min 0.3mm width and 0.2mm clearance ?

[Tesla DeLorean]

Posted on November 14, 2014 at 18:41

None of your external signals are going to exceed 90 MHz. Pay attention to your supply layers, placement of bulk capacitance, decoupling caps and current flow paths.

For BGA designs be very conscious of via-in-pad, that they are suitably filled, and planerized. Watch for the shrink in the solder mask when placing wires close to pads, and for solder to bridge between uDFN pads.

[mrniknejad]

Posted on November 17, 2014 at 19:42

Hi again

thanks for your reply but are you sure about the max IO frequrncy (90 MHz) ?because i have an SRAM in my design !thanks again

[mrniknejad]

Posted on November 23, 2014 at 12:57

Hi 

help pleeeeease !!!!

[John F.]

Posted on November 24, 2014 at 15:45

The rate of change of the signal ''transition time'' and the length and type of conductor you're trying to send it down are the critical things. ST don't seem to provide much guidance but you could have a look at Freescale Semiconductor's Application Note AN2536 and Analog Devices Tutorial MT-097 (Google them).

You may need to find a hardware engineer to help you. Look at the signal timings of the SRAM and the microcontroller signals to get a feel for how critical it might be (or how slow you're going to have to set the bus). As a guide, I have an STM32F429 running at 180MHz with 143MHz 7ns SDRAM connected. The PCB designer took care to equalize the signal and data track lengths (about 2'' ( 50mm ) in length) but apart from using a solid ground plane and tight decoupling no other special measures taken (no termination used for example). I don't think you're going to get much more specific advice.