STM32F407

[NEERAJ GUPTA]

Posted on April 13, 2017 at 06:44

Dear Sir,

               I m using timer1 of STM32F407 to get Edge-aligned PWM & using the following settings to give 84 MHz clock to timer1 :

RCC->PLLCFGR &= ~(0x1F); //PLLM=0    

 RCC->PLLCFGR |= 0x08; //PLLM=8 RCC->PLLCFGR &= ~(0x7FC0); //PLLN=0     RCC->PLLCFGR |= (84)<<6; //PLLN=84 RCC->PLLCFGR |= 0x010000; //PLLP=4 RCC->PLLCFGR |=(4)<<24; //PLLQ=4     RCC->CR |= RCC_CR_PLLON;      while((RCC->CR & RCC_CR_PLLRDY)==0); //stay here if PLL not ready     RCC->CFGR |= 0x0000002; // PLL selected as system clock

Basic steps followed:

1. HSI internal (16 MHz) is chosen as oscillator.

2. PLLM is set to 8.

3. PLLN is set to 84.

4. PLLP is set to 4.

5. PLL is switched ON.

6. PLL is checked whether it is locked properly.

7. System clock input source MUX selects  PLL as input.

8. PPRE2;PPRE1;HPRE in RCC_CFGR register are left to their default values.

As per my application, i need PWM frequency more than 16 MHz. Which i m not getting even after entering these settings.  Even this 16 MHz PWM is not stable enough. Please! provide the required correction.

[Nesrine M_O]

Posted on April 13, 2017 at 10:45

Hi

GUPTA.NEERAJ

,

I'd highly recommend you to start from Timerexamples under the

http://www.st.com/content/st_com/en/products/embedded-software/mcus-embedded-software/stm32-embedded-software/stm32-standard-peripheral-libraries/stsw-stm32html

STM32F4xx_DSP_StdPeriph_Lib_V1.8.0\Project\STM32F4xx_StdPeriph_Examples\TIM, it can be very useful.

-Nesrine-

[Tesla DeLorean]

Posted on April 13, 2017 at 11:32

At high frequencies you'll need to select a PLL clock that is cleanly divisible by the output clock you want. For 16 MHz try 128 MHz 

[NEERAJ GUPTA]

Posted on April 13, 2017 at 11:09

Hi Nesrine M,

                      i have already completed this exercise as mentioned by you using 

STM32F4xx_DSP_StdPeriph_Lib_V1.8.0

.

I have also generated the required code using STM32 CUBE MX. But still the result is same.  Please! provide the required corrections .

[NEERAJ GUPTA]

Posted on April 13, 2017 at 13:10

Dear Clive,

                  i m able to achieve upto 16 MHz using PLL clock as advised by you. But my requirement dictates PWM  frequency > 16 MHz. I m not able to go above this frequency. Please! advise to how achieve this.   

[Tesla DeLorean]

Posted on April 13, 2017 at 14:59

I'm saying the PLL clock needs to be an integer multiple, as the TIM can only do integer division

If you clock the PLL/CPU at 168 MHz, you could get a 21 MHz or 42 MHz PWM signal, but you won't be able to have much control of the pulse width due to the small number involved.

ie If you divide the TIMCLK by 4, you options would by a duty cycle of 0%, 25%, 50% and 75%