2014-04-28 05:48 PM
Hi all,
I have read section 2.1.10 in the errata over and over without really getting the message.http://www.st.com/web/en/resource/technical/document/errata_sheet/DM00037591.pdfDo the fine people at ST mean that DMA2 can only serve one task at the time, ie I can not have concurrent DMA transfers despite all fancy hardware, multiple buses, arbiter etc, described in the reference manual? Do they mean that I have to use the CPU to shuffle data if I have more than one stream? I hope I'm wrong and have misunderstood the situation completely.Any thoughts on this? #stm32f407-dma2-errata2014-04-29 12:25 AM
As far as I understand the errata, all APB transfer are OK and can be done concurrently.
On the other side, AHB transfers suffers from duplicate accesses (eg.reading twice from the same location). This does not hurt that much when the target is memory. But when you have a FIFO based access through AHB, the issue become critical. In others words, you cannot use DCMI DMA concurrently with APB transfers. The same situation happens with CRYPTO, HASH or any FIFO based device connected though FSMC. What are the concurrent DMA you plan to enable ? -- laurent2014-04-29 03:51 AM
The setup is:
DMA2 stream 2 very high priority for ADC2 to internal RAM.DMA2 stream 5 medium priority for copying data back and forth between internal RAM and external RAM ''on demand''.So far I don't get any errors.I get 100% transfer errors when I add:DMA2 stream 0 high priority for copying data from internal RAM to external RAM periodically (32 bytes at 2048Hz).2014-04-29 04:13 AM
This setup is apparently not impacted by the problem depicted in errata.
Transfer error happen as well when there is a bus error. Could it be the same problem that JW highlighted (accessing CCM) ?2014-04-29 05:31 AM
Correct, the very same problem. Solved and works like a dream.
But I still think the errata is a bit unclear...