STM32F407 and TDM or multiline I2S (DAC/ADC)

[enc0der]

Posted on August 27, 2013 at 23:08

Hello!

I've been wanting to increase the ADC/DAC setup in my design using the STM32F407 chip but I am having a hard time understanding what specific functionality I can use to get more than 2 in / 2 out over a single I2S implementation. Given that the evaluation board was using the Cirrus Logic DAC (and ADC) I started looking at their other solutions which I found quite a few that I liked.  Unfortunately, I found that if I wanted to use I2S, that each stereo pair comes out it's own separate data line.  I don't see any mechanism within this STM32 chip to support parallel I2C data sends.  The next thing I saw is that most of their chips do 256xFs TDM mode (also called DSP mode by some manufacturers it looks like) but I cannot figure out how I would use TDM without just using bit-blasting which then would most certainly mean I cannot use DMA transfers to free up the processor. Clearly I must be missing something here.  Also, I don't understand why I2S2 and I2S3 are on the same DMA channel?  I would think I'd like them to both go in and out at the same time.  Unless the memory access is so fast, that they can work concurrently since I2S is so much slower they just sort of interleave on their own. Any suggestions? What I was trying to use is CS5366 ADC (6 channel ADC in) and  CS4365 (6 channel DAC out).  Not even sure if there is like a TDM to I2S converter (both direction) that I should be considering.  I searched quite a bit on these things and found nothing. Thanks for taking a look! Rick

[Tesla DeLorean]

Posted on August 28, 2013 at 03:04

Also, I don't understand why I2S2 and I2S3 are on the same DMA channel?

Don't confuse Channels and Streams, the channel is an input source mux to the streams. The streams are the individual working units within the DMA controller.

[enc0der]

Posted on August 28, 2013 at 04:15

Okay, I clearly am then! Thanks for the pointer.  The documents are just not 100% clear to me, might be time to pick up one of the M4 cortex books that people have talked about on here.

I just don't see anything that talks about multiple data line I2S support so I'm back to researching TDM to I2S conversion.  What I am thinking is if I can figure that out, then I can get the data in through DMA on the I2S busses concurrently and that should be good for me.

[Tesla DeLorean]

Posted on August 28, 2013 at 04:46

The problem with most of the books is that they focus on the core/processor, and not the unique peripherals each manufacturer attaches to them. I'd recommend Joseph Yiu's books to complement the ARM documentation, and ST's. He has a new M3/M4 book scheduled for mid November.

The new F42x core has an SAI (Serial Audio Interface) which supports TDM.

http://www.st.com/st-web-ui/static/active/jp/resource/sales_and_marketing/promotional_material/brochure/brstm32f4.pdf

Main features �? Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO. �? 8-word integrated FIFOs for each audio sub-block. �? Synchronous or asynchronous mode between the audio sub-blocks. �? Master or slave configuration independent for both audio sub-blocks. �? Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. �? Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. �? Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 �? Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame. �? Number of bits by frame may be configurable. �? Frame synchronization active level configurable (offset, bit length, level).

[enc0der]

Posted on August 28, 2013 at 05:24

I figured that would be part of the problem with a lot of the ARM books.  I did find the new version they released, that said, I'm not seeing any for sale and also wondering if they are gonna do a similar eval board for it like the STM32F407.  It's looks perfect though.  From the datasheet it seems like I'd be able to use both internal blocks to do TX and RX TDM at the same time using DMA which is what I want.

Any clue when these will be available?  The other interesting problem will be I am using the ChibiOS code base which I'll most certainly have to hack up to use this new processor.  Just surprised i find really nothing about interfacing TDM to the STM32F407 variant.