Skip to main content
michalik
michalik
Associate
July 24, 2015
Question

STM32F401VB - Clock Idle State of SPI Interface does not stay high

  • July 24, 2015
  • 11 replies
  • 4536 views
Posted on July 24, 2015 at 11:09

Hey guys!

I have an issue with the SPI Interface of the STM32F401VB. To communicate with an ADC from LTC, I need to configure the SCK to stay high during idle time. Unfortunately the clock always starts low, see scope pictures. Where exactly is the problem? Do I need any pull up resistors or something ?

Thanks in advance for your help!

Best regards

David

    This topic has been closed for replies.

    11 replies

    Show previous replies
    waclawek.jan
    waclawek.jan
    Super User
    July 24, 2015
    Posted on July 24, 2015 at 15:52

    > Sorry my mistake.. the uC is the master but in receiving mode. so there is only data on the MISO line.

    I see.

    I am confused. I've scoped the SPI lines a zillion times and don't remember experiencing hi-Z CLK - never looked deliberately, though, and there might've been enough parasitic capacitance to keep it high between transmissions.

    JW
    Terms & ConditionsAccessibility statement