STM32F4 SPI - RXNE never gets asserted.

[gustavodealmeidamartins]

Posted on June 20, 2015 at 20:02

Hi,

I am debugging the SPI interface on the STM32F427 for a while now. I am using SPI1 and SPI2. SPI1 works just fine, I am able to transmit and receive data just fine. Now I am struggling to get SPI2 to work fully.I can see SPI2 clock on the bus and data on MISO and MOSI lines. RXNEIE even gets asserted but RXNE never does.Reading the manual I could confirm that :-RXNEIE set means that the receive buffer is not empty-RXNE set means that data were transferred from the shift registerto the Rx buffer.What am I missing here? What usually causes the data sitting on the receive buffer to be not valid?I am not sure what my next step debugging should be. Any suggestion is more than welcome.  

[Tesla DeLorean]

Posted on June 20, 2015 at 20:25

Well looking at the SPIx->DR in a debugger is going to clear RXNE in the SPIx->SR

Would suggest you show your code so there's some chance of understanding what's going on in your situation.

[gustavodealmeidamartins]

Posted on June 20, 2015 at 21:19

My issue is that the RX interrupt is triggered but the RXEN never gets asserted. See the image thatRXNEIA is asserted, the SR register should be 0x0001 but it is 0x0002 and it does not change. What portion of code would like to see based on what I have described so far?

________________ Attachments : SPI_Int_Handler.JPG : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HzPC&d=%2Fa%2F0X0000000bLS%2FFaKphLQbscOYYtFfn3xuC7LDZbja_LPcXCM6FQs6_wI&asPdf=false

[Tesla DeLorean]

Posted on June 20, 2015 at 22:01

Close the peripheral view on the right, it's invasive. Break point and step the code without it.

RXNEIE is an enable bit in a register, it being set is not impactful as to whether RXNE asserts in the SR