In a short investigation of postings related to internal PLL-output usage to supply a clock to a LAN8720A, this one fits perfectly to discuss my experiences.
I have designed a board with F407 and in order to be able to update firmware via the USB bootloader I am forced to use a crystal < 16 MHz (I chose 12 MHz). Therefore I have set up I2S PLL to output 25 MHz. This runs quite wel, until... two board samples from a small proto test batch showed spurious connection issues (e.g. ping packet loss).
I felt safe by Refmanual (RM0090) 33.4.2 section "MII clock sources", where PLL usage is mentioned. And that should not depend on MII or RMII. Above that, PLL usage with other MCU (e.g. NXP) is quite a usual practice.
After problems arose, I found the following interesting hint in the RM: It is recommended to select a frequency of 2 MHz to limit PLL jitter. (I realized that 1 MHz is indeed quite low compared to other MCUs that I used)
After scaling up to 1.5 MHz (from 1 MHz), the connection issues disappeared. Then I selected 2 MHz and as expected, the result is also okay, but should be expectedly more reliable, also at elevated temperature. Note: in the "problem" case, the link activity LED blinks quite rapidly also when no connection is made. I obeyed that applying freeze spray on the MCU casing let the LED blink normally (apparently, the jitter increases with temperature).
Given the apparent headroom at 2 MHz PLL input clock, I tend to treat that as sufficient.
(more/other detailed infos on Microchip forum - due to LAN87xx being theirs: https://forum.microchip.com/s/topic/a5CV40000001rYXMAY/t397529)
