2012-04-10 02:05 PM
Hi all,
With Keil MDK-ARM I had a random hard fault when I change the optimization level of the compiler. The reason is a VPUSH.64 assembler instruction that tries to use the FPU. This instruction is added by the compiler before entering the main() function, so, at this point, the PFU is not enable. I found a solution at http://e2e.ti.com/support/microcontrollers/stellaris_arm_cortex-m3_microcontroller/f/471/t/155025.aspx?PageIndex=2 Edit startup_stm32f4xx.s file and add the following code in the Reset_handler ; CPACR is located at address 0xE000ED88 LDR.W R0, =0xE000ED88 ; Read CPACR LDR R1, [R0] ; Set bits 20-23 to enable CP10 and CP11 coprocessors ORR R1, R1, ♯(0xF << 20) ; Write back the modified value to the CPACR STR R1, [R0]; wait for store to complete DSB ;reset pipeline now the FPU is enabled ISB Regrds, �ngel #semihosting2013-10-02 04:16 AM
My investigations indicate
- can't use MICROLIB if you want to use C++ - have to use MICROLIB if you want to use ITM (i.e. printf) So result is - can't use ITM (i.e. printf) if you want to use C++ Workarounds are all well and fine but there comes a point when you can't actually do what you need to do. In most cases a proper fix is better.2013-10-02 05:26 AM
ITM/SWV work at a hardware level, you are complaining about the libraries you are using, and how they are tailored to your platform. How you resolve your hosting issue is between you, the documentation, and Keil support.
2013-10-02 08:31 AM
2013-10-02 09:01 AM
http://www.keil.com/support/man/docs/armccref/armccref_bgbjjgij.htm
http://www.keil.com/support/man/docs/ARMCCREF/ARMCCREF_CHDJHHDI.htm
http://www.keil.com/support/man/docs/ARMLIB/armlib_Cihibfib.htm
http://www.keil.com/support/man/docs/ARMLIB/armlib_CJAECCHH.htm