Posted on August 11, 2015 at 22:44I'm sure the map memory is described in those manuals. If not there look at the Cortex-M3/M4 technical reference manuals, or books by Joseph Yiu. Perhaps a book on micro-processor architectures might be useful too.
The memory is 32-bit addressable, giving an access range of 4GB, you read/write ANY memory just like ANY other, the access is design to appear uniform, although different areas may run at different speeds, and be on different buses. The memory is sub divided in to regions, to permit easy decoding with logic gates, the high order 4-bits being of particular merit in the Cortex-Mx family, and providing for 16 regions.
The FLASH memory is situated at 0x08000000, the SRAM at 0x20000000, and CCMRAM at 0x100000000, SDRAM at 0xC0000000/0xD0000000, Peripherals at 0x40000000, External RAM/NAND/NOR 0x60000000
The processor boots from 0x00000000, and does so using logic associated with the BOOTx pins to ''shadow'' FLASH, ROM or SRAM at this ZERO based address. Shadowing mean when an access is decoded in either region the memory that's enabled and functioning is the same.
If the FLASH is 1MB in size it spans 0x08000000 to 0x080FFFFF, if you touch 0x08010000..0x08FFFFFF it's going to Hard Fault the processor because it's know's there's nothing there, the decode logic tell's it no one is claiming ownership of it. So within the 4GB there can be voids, and this isn't a problem because 4GB is a lot of space, and in the simple embedded micro would just complicate things.
