2018-07-26 12:21 PM
We are running TIM3 and TIM2 on a STM32F303ZE processor generating pulses on both timer outputs synchronous to an external input trigger. We have TIM3 configured for “Trigger Mode�? with the “External Trigger�? selected running in “one pulse mode�?. TIM2 is slaved to TIM3-TRGO which is selected as TIM3 Count Enable. The output pulses are generated on TIM3-CH2 (Retriggerable OPM mode 2) and TIM2-CH1 (PWM Mode 2).
The configuration works as expected when an external trigger is present. I would like to occasionally “trigger�? the pulses manually by writing the TG bit in the TIM3_EGR register but this does not work. It doesn’t even cause the TIM2 slave to trigger.
I ran a couple experiments.
1) By setting the counter enable bit in TIM3 CR1-CEN, TIM2 CH1 will generate it’s output pulse however, TIM3-CH2 does not generate an output pulse.
2) I re-ran the first experiment but instead of running TIM3-CH2 in Retriggerable OPM mode 2 (9), I ran it in PWM mode 2 (7) and set CCR2 to 1. When I set the TIM3 counter enable bit, the TIM3-CH2 output changes meaning that simply starting the TIM3 counter does not enable the CH2 output channel when configured for Retriggerable OPM mode 2. Unfortunately, running in PWM mode 2 is no good since I need to set CCR2 to a non-zero value in order to generate a pulse and this delays the generated pulse.
Why does writing of the TG bit in the timer 3 event register not trigger output pulses on TIM3-CH2?
Original TIM3 Configuration
CR1-UIREMAP = 0
CR1-CKD = 0
CR1-ARPE = 1
CR1-CMS = 0
CR1-DIR = 0
CR1-OPEM = 1 (one pulse mode)
CR1-URS = 0
CR1-UDIS = 0
CR1-CEN = 0
CR2-TI1S = 0
CR2-MMS = 1 (TRGO = CNT_EN)
CR2-CCDS = 0
SMCR-ETP = 0
SMCR-ECE =0
SMCR-ETPS = 0
SMCR-ETF = 0
SMCR-MSM = 1 (master mode enable)
SMCR-TS = 7 (external trigger input ETRF)
SMCR-OCCS = 0
SMCR-SMS = 6 (Trigger Mode)
CCMR1-OC2M = 9 (Retriggerable OPM mode 2)
CCMR1-OC2CE = 0
CCMR1-OC2PE = 0
CCMR1-OC2FE = 0
CCMR1-CC2S = 0
CCER-CC2NP = 0
CCER-CC2P = 0
CCER-CC2E = 1 (enable CH2 output)
CNT = 0
PSC = 0x167
ARR = 40000
CCR2 = 0 (no delay)
Thank you!
2018-08-09 08:30 PM
@ST Community any FAEs want to cover this?