STM32F3 Opamp needed guidance

[melchor]

Posted on January 30, 2013 at 11:16

In an application using the STM32F3xx, I am using the OPAMP in PGA mode to amplify an external 1 kHz signal to the ADC converter. The signal is provided AC coupled to the OPAMP non-inverting input.

If I program the OPAMP in follower mode everything works fine. The ADC reads the right values and the signal in the OPAMP output pin is correct and centered around VDDA/2. However, if I program for PGA mode and specially with higher gains, the OPAMP works erratic. In some cases the output is clipped around VDDA and sometimes around VSS. Probing with the oscilloscope in the OPAMP output pin, has effect in the behaviour and sometimes it makes it working fine. I am wondering in the non-inverting configuration, what is the VREF level used and if it is programmable. What I see it is a bit the lack of information and examples about the use of the OPAMP with the std peripheral library, e.g. for the calibration and for the VREF settings. Any additional guidance on the OPAMP operation of hints about what could be the source of this problem, will be of great help. #stm32f3-opamp

[frankmeyer9]

Posted on January 30, 2013 at 13:10

You might not have noticed yet, but there is a STM32F3 version of the standard peripheral library, with opamp examples in the folder

...\STM32F30x_DSP_StdPeriph_Lib_V1.0.0\Project\STM32F30x_StdPeriph_Examples\OPAMP\...

It contains also one PGA example. That may already answer some of your questions.However, if I program for PGA mode and specially with higher gains, the OPAMP works erratic. In some cases the output is clipped around VDDA and sometimes around VSS. That also depends on your input signal.For full output swing, it should be centered around VDDA/2, (assuming VDDA/2 as virtual ground). Shifting either your signal or the virtual ground will easily clip the output signal. Probing with the oscilloscope in the OPAMP output pin, has effect in the behaviour and sometimes it makes it working fine. Perhaps you have a noise problem due to non-optimal layout. Honestly, I have not yet worked with the internal opamps, so you might need to consult the datasheet about sensitivity and feedback/compensation requirements.

[melchor]

Posted on February 03, 2013 at 18:56

I think that the basic problem is that the STM32F3 opamps are not specifically tailored for AC coupled signals in PGA mode. The programmable gain network is DC connected directly to GND and there is no way to change it.

[frankmeyer9]

Posted on February 04, 2013 at 09:30

I agree with you.

And albeit it's probably a technical challenge to implement an opamp running with 3 .. 3.3V, its parameters are nonetheless significantly worse than separate devices at higher supply voltages. I'm using an external signal conditioning, and generate the negative supply voltage for the opamp(s) with a icl7660 device.

[jerzy23]

Posted on February 04, 2013 at 11:01

Hello,

I have the same problem with STM32F3, I have blocking-capacitor coupled signal on the non-inverting input, and the signal on the op-amp side is pulled to VDDA/2 by 50kOhm resistor. In other words, the signal on the PA7 is always in correct range 0-3V, but after enabling PGA it always appears clipped. So what is the correct circuit to make the PGA with external low-pass capacitor work? My application depends on this . . .

[frankmeyer9]

Posted on February 04, 2013 at 12:13

I have blocking-capacitor coupled signal on the non-inverting input, and the signal on the op-amp side is pulled to VDDA/2 by 50kOhm resistor.

In other words, the signal on the PA7 is always in correct range 0-3V, but after enabling PGA it always appears clipped. I assume you mean the reference, i.e. inverting input of the opamp is connected to VDDA/2. You do not need to do this, but most often the opamp parameters are worse when referencing to a value near the rails. I hope you are aware of the fact that an opamp amplifies the voltage difference between V(-) and V(+), so when you use 0V...3V and set a gain of > 1, you will certainly get a clipped output. You might try to set the inverting input to AGND, and possibly use a resistive divider to scale the signal down. But as said, usually opamp behavior is nonliniear close to the rails, and the frequency response also deteriorates.

[Tesla DeLorean]

Posted on February 04, 2013 at 13:37

My application depends on this . . .

Critical design aspect outsourced to random dudes on the internet, priceless.

[jerzy23]

Posted on February 04, 2013 at 17:52 Do you not have any better thing to do?

[jerzy23]

Posted on February 04, 2013 at 18:00

OK i have a solution to this problem.

To the useless trolls: The frequency response is not an issue because this op-amp has a rated bandwidth of 8MHz, so at gain=16 i still get over 100kHz (~500kHz?) usefull bandwidth. Not an issue in an application that requires sampling of 4kHz. (my signals are up to 200Hz . . .)The solution for the rest of us is: Due to the way the internal PGA resistors are connected, the 'middle level' of the output signal shifts with gain. This means that for gain=2, the signal has to be centered around 375mV, gain=4-> 188mV, Gain=8 ->94mV and Gain=16 -> 48mV. This can be achieved by simply using one of the DAC channel in constant voltage output mode. Simply connect the DAC output (using buffer and prefferably, also 1:4 voltage divider) as your 'biasing source' and then adjust DAC output level depending on the gain. The software driver of the OPAMP uses some werid names for inputs. In case if You wondered, for opamp-1, to use PA3 as the negative input feedback, use ''OPAMP_PGAConnect_IO2'' in command: OPAMP_PGAConfig(OPAMP_Selection_OPAMP1, OPAMP_OPAMP_PGAGain_2, OPAMP_PGAConnect_IO2); Regards, Jerzy

[jerzy23]

Posted on February 05, 2013 at 09:24

Correction:

* Its INPUT middle level that shifts * the DAC divider has to be 1:2 so that it can cover full range from gain=1 to gain=16 Jurek