STM32F207 FSMC Bus Turnaround timing

[fpeelo]

Posted on May 29, 2014 at 16:15

I need some help in understanding the Bus Turnaround time of the FSMC. I think I have it right, but don't want to burn out the data bus in finding out I'm wrong. Could someone who knows, confirm please?

My STM32F207 has a slow device and a fast SRAM connected to the address and data buses. They are accessed with the basic SRAM Mode 1 shown in section 31.5.4 of RM0033 using NE1 and NE2 respectively.

• According to ''Table 174. FSMC_BTRx bit fields'' in the Mode 1 description, BUSTURN controls ''Time between NEx high to NEx low (BUSTURN HCLK)''

The description of the BUSTURN field in FSMC_BTR1..4 says: (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if EXTMOD = �0� (It does say BUSTRUN. I didn't mistype that.) So is the time between NEx high to NEx low BUSTURN HCLK or (BUSTURN+1) HCLK? I think it has to be (BUSTURN+1) HCLK, otherwise I don't see hwo NEx would ever go high if BUSTURN was 0. In other words, NEx will always go high for one HCLK, and BUSTURN extends this. Is this correct?

• In all the timing diagrams, the data bus is driven for a short time after NEx goes high. For the external devices on the bus, this time is in the datasheet. If the FSMC is driving the bus, I cannot find the time value (tEHEL min, presumably). Would it be within 1 HCLK?

• I am 99% sure that if I do a read on NE1 with BUSTURN=8, and then a read on NE2, that there will be 9 HCLK between NE1 going high and NE2 going low. In other words, when RM0033 says ''Time between NEx high to NEx low'', the two NEx don't have to be the same line. Is this correct? 

If not, is it possible to have devices of different speeds attached, and not run them all at the speed of the slowest? Many thanks #stm32f207-fsmc

[waclawek.jan]

Posted on May 29, 2014 at 17:25

My experience is with '40x, but IMO it will be the same as far as FSMC is concerned.

The description of most of the peripherals in the manuals is very sloppy; the description of the registers is usually better, although those are far from being precise, too. > (It does say BUSTRUN. I didn't mistype that.) :) . In fact, :( . > I think it has to be (BUSTURN+1) HCLK, Yes it is. In this thread https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/AllItems.aspx?RootFolder=%2Fpublic%2FSTe2ecommunities%2Fmcu%2FLists%2Fcortex%5Fmx%5Fstm32%2Fmemory%20with%20long%20write%20recovery%20time%20with%20FSMC%20of%20STM32F407IG  a related timing issue is discussed (address/data hold when write), I posted some waveforms there. > In all the timing diagrams, the data bus is driven for a short time after NEx goes high. It is irrelevant. In fact, the data timing is derived from NWRx, which goes high one clock before NEx, and data hold is 1 clock, so there is no real hold from NEx going high. You can infer some of the timing from th(NE_NWE) and th(Data_NWE) from the Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms (I haven't had a look into the '20x datasheet, but this is in '40x datasheet and I guess this is a copy/paste situation). You can't see these in the waveform I posted in the abovementioned link, as the data bus there is floating until the next transaction, and the parasitic capacitances hold the previous level long enough. > I am 99% sure that if I do a read on NE1 with BUSTURN=8, and then a read on NE2, that there will be 9 HCLK between NE1 going high and NE2 going low. > In other words, when RM0033 says ''Time between NEx high to NEx low'', the two NEx don't have to be the same line. Is this correct?  Hard to say. If you perform a NE1 write followed by NE2 write, either the NE1's BUSTURN may apply, or NE2's, or both consecutively, or the smaller or the bigger of the two - the manual does not answer this. I'd recommend you to experiment, e.g. with a Discovery board - you don't actually need to have a memory attached to see the address/data/control signals' timing - run it at low speed to clearly see the timings on an oscilloscope. And please come back with your findings. Thanks, Jan Waclawek