STM32F205 quiescent current under reset

mailmail9117 · ‎2013-03-21

Posted on March 22, 2013 at 00:42

I am holding an STM32F205 in reset (NRST pin low). I am measuring the current into VDD1-4 plus AVDD at 1.7mA. I am using 3.3V.

0.1mA I can explain through the pull-up resistor on the NRST pin per datasheet.

0.3mA I [think I] can explain through the AVDD pin quiescent current per datasheet.

I was expecting the remainder of the quiescent current to be closer to the current listed in the datasheet under ''standby'' (<0.1mA). How much current should the STM32F205RC take while held in reset?

#stm32f2-power-standby-reset

waclawek.jan · ‎2013-03-22

Posted on March 22, 2013 at 16:36

I'd expect that during system reset the chip is in the Run mode with HSI as the system clock, all registers in default state (which implies all peripheral clocks off) and the ARM core being held in some non-working state, which implies no activity on the buses (that would yield a similar consumption than in Sleep mode(?)). My reasoning is, that if the chip should start off executing immediately after reset is released, the regulator should be already up an running and so should be the default clock (i.e. HSI). That precludes as low consumption as in Stop/Standby.

I can't find anything relevant in the available literature though. Would be interesting to hear from ST on this.

JW