STM32F10xx FSMC Wait Signal

[christophrecht9]

Posted on July 11, 2012 at 16:59

Hello,

in the Document RM0008 (datasheet of the STM32F10xx Family) on Page 510 is the FSMC access described with the external WAIT Signal. It works well for my application now, but i have some problems by understanding the timing issue. There are two timings in the diagramm: adress phase and data_setup phase. My configuration is Mode B. Does this mean i can change the length of adress phase with the ADDSET register? Is this also (ADDSET+1)? Same for the data_setup phase? data_setup phase = (DATASET+1) ? I'm also confused with the meaning of the max_wait_assertion_time.

Memory asserts the WAIT signal aligned to NOE/NWE which toggles:

data_setup phase >= 4 * HCLK + max_wait_assertion_time

Description:

Where max_wait_assertion_time is the maximum time taken by the memory to assert the

WAIT signal once NEx/NOE/NWE is low.

Is it the time, after NEx/NOE/NWE  ist active, the memory need to bring the WAIT Signal to BUSY level (low) or the maximum time the memory is BUSY(low)?

My first thought was, that the adress phase controls the sample time of the WAIT signal and after the WAIT signal isn't BUSY the data_setup phase begins. But my measurements of the time are not equal to the settings. Example: tHCLK = 10ns DATASET = 4 (+1) = 5 After the WAIT signal isn't BUSY (rising edge) the memory access duration ist about 50ns. But i see it takes 80ns? Need some more explanation here. Thanks, Christoph Recht #stm32-fsmc-wait-adress-setup

[Tesla DeLorean]

Posted on July 11, 2012 at 17:23

Not to be obtuse but how are you getting a 100 MHz clock (10ns) from a 72 MHz part?

A minimal 5 cycle interaction would be 69.44 ns, 6 would be 83.33 ns

[christophrecht9]

Posted on July 11, 2012 at 17:37 it was only a example. Sure it is 13,89ns but i think it is easier to calculate with 10ns. the 80ns are also not really 80. Real Values are: DATASET = 4 , time = 102ns sorry, thanks

[Tesla DeLorean]

Posted on July 11, 2012 at 18:10

It's going to depend on your internal clock settings.

The way I read the documentation the minimum (ie no NWAIT)  NEx/NOE asserted is 6 cycles, with NWE asserted for 5 cycles on writes. If NWAIT ever asserts (as sampled at +2 cycles) you're going to be at least 7 cycles. The next memory access will be at least 1 cycle away. Are you measuring the NEx pulse width here? Specify this width, and your clock settings. The documentation is a bit cryptic, but I could see the address phase being at 3 cycles, depends on ADDHLD (min=1 ?) and ADDSET. So 7 or 8 cycles for NEx are not inconceivable. What parameters are you programming, and to what?

[christophrecht9]

Posted on July 12, 2012 at 10:23

thanks clive,

first here ist my  working FSMC configuration:

// Read Timing

r.

FSMC_AddressSetupTime

= 1;

//1

r.

FSMC_AddressHoldTime

= 0;

//0

r.

FSMC_DataSetupTime

= 4;

// 2

r.

FSMC_BusTurnAroundDuration

= 0;

r.

FSMC_CLKDivision

= 0;

r.

FSMC_DataLatency

= 0;

r.

FSMC_AccessMode

= FSMC_AccessMode_B; // WRITE Timing

w.

FSMC_AddressSetupTime

= 1;

//1

w.

FSMC_AddressHoldTime

= 0;

//0

w.

FSMC_DataSetupTime

= 4;

// 2

w.

FSMC_BusTurnAroundDuration

= 0;

w.

FSMC_CLKDivision

= 0;

w.

FSMC_DataLatency

= 0;

w.

FSMC_AccessMode

= FSMC_AccessMode_B;

FSMC_NORSRAMInitStructure.

FSMC_Bank

= FSMC_Bank1_NORSRAM4;

FSMC_NORSRAMInitStructure.

FSMC_DataAddressMux

= FSMC_DataAddressMux_Disable;

FSMC_NORSRAMInitStructure.

FSMC_MemoryType

= FSMC_MemoryType_SRAM;

FSMC_NORSRAMInitStructure.

FSMC_MemoryDataWidth

= FSMC_MemoryDataWidth_16b;

FSMC_NORSRAMInitStructure.

FSMC_BurstAccessMode

= FSMC_BurstAccessMode_Disable;

FSMC_NORSRAMInitStructure.

FSMC_AsynchronousWait

= FSMC_AsynchronousWait_Enable;

FSMC_NORSRAMInitStructure.

FSMC_WaitSignalPolarity

= FSMC_WaitSignalPolarity_Low;

FSMC_NORSRAMInitStructure.

FSMC_WrapMode

= FSMC_WrapMode_Disable;

FSMC_NORSRAMInitStructure.

FSMC_WaitSignalActive

= FSMC_WaitSignalActive_DuringWaitState;

FSMC_NORSRAMInitStructure.

FSMC_WriteOperation

= FSMC_WriteOperation_Enable;

FSMC_NORSRAMInitStructure.

FSMC_WaitSignal

= FSMC_WaitSignal_Enable;

FSMC_NORSRAMInitStructure.

FSMC_ExtendedMode

= FSMC_ExtendedMode_Enable;

FSMC_NORSRAMInitStructure.

FSMC_WriteBurst

= FSMC_WriteBurst_Disable;

FSMC_NORSRAMInitStructure.

FSMC_ReadWriteTimingStruct

= &r;

FSMC_NORSRAMInitStructure.

FSMC_WriteTimingStruct

= &w;

FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);

/* BANK 4 (of NOR/SRAM Bank 1~4) is enabled */

FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4,

ENABLE

); i have another idea how the data_setup time is calculated. The formular is:

data_setup phase >= 4 * HCLK + max_wait_assertion_time

4 * HCLK is shown in the diagramm, so my first thought was, that i can set DATAST to 3 (+1) = 4 und so i have this constellation. But i get read errors. With DATAST = 4 (+1) = 5 all seems to work fine. With the DATAST = 3 configuration i see on the LA that the FSMC ends the read access always before! the WAIT signal goes to READY. Now my suggestion: the max_wait_assertion_time is the time the memory needs for the ''slowest'' access. if data_setup phase is expired and the wait signal is not READY the FSMC quits the access. This is what i see with the logic analyser and makes sense. So it is like a timeout? But i measure the time the WAIT signal is BUSY, it's about 100ns. So DATAST should be 7 (+1) = 8, means 111ns to not run in a timeout, but with DATAST = 4 (+1)  = 5 it works? This means only 70ns and should also run in a timeout? Don't get me wrong it all seems to work fine, but i get this values by try&error and can not legitimate them with the datasheet. Also i measure another behavior as i have configurated. So it works, but why? Greetings from Germany (sorry for my english) Thanks, Christoph Recht

[Tesla DeLorean]

Posted on July 12, 2012 at 12:42

Can you present the measurements you have made, ideally in a timing diagram or scope capture form.

Thanks.

[christophrecht9]

Posted on July 12, 2012 at 12:58

ok here:

Green = Write access with DATAST = 4, this works Red = Read access with DATAST = 3, FSMC quits access and don't wait for the WAIT. if i switch DATAST in the READ timing configuration to 4 it works like the GREEN (Write) Access. i need to know what ist data_setup phase (DATAST or DATAST + 1?) and WHEN it starts and what ist ment by the formula. i measured a WAIT signal length (max. ~ 2us!) an with DATAST = 3 i get a timeout, with DATAST=4 ist works? So it not seems to be a timeout? I'm very confused... thanks ________________ Attachments : ready_datasetup_time_zu_kurz.png : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtVQ&d=%2Fa%2F0X0000000aQz%2FMKIhHrNB67xMDjtwMJGcmnM4GVxsIIxQeRS19ko2riU&asPdf=false