stm32f103vbt6 Interrupt Numbers ?.

[Chris Quayle]

Posted on July 20, 2017 at 00:15

Evaluating the above processor using gcc toolchain and openocd and J-Link. Not using cmsis (various reasons) and writing all the low level hal and header files, as a way to become more familiar with the processor. Already have  a simple non interrupt based program running, but need to understand the relationship between the interrupt numbers for the device and how these are derived. From what I can see, each device has a different set of interrupt numbers to control access to the nvic, but can find no docs that define that, after extensive web search and scan of the device data sheets etc. Would assume that this has been defined and docs must exist somewhere ?...

Regards,

Chris

[Chris Quayle]

Posted on July 22, 2017 at 01:00

Many thanks for all the replies. Later this evening I found a github page for the core_cm3.c and core_cm3.h files. Old version of CMSIS, but no matter. The  functions are defined in the header file, so can now see exactly what the translation is. One line of code, in fact. I know all the variants are different, but the nvic access method looks generic to all, with the interrupt number being the key. Perhaps update the docs in future to include this ?, as the algorithm is not obvious without seeing example code. Constant feedback and improvement etc :-).

You may ask why we are writing our own hal layer. We are currently evaluating various arm processors for future projects and the ST M3 series looks ideal. The only way to really understand the device is to write the hal layer.  Also, to find limitations and / or gotchas, this being the only example so far. The investment in time is more than worth the effort over a set of projects and provides a completely transparent audit trail for code from the top right down to bare metal. Something that's important for many clients, as well as being the due diligence part of the work . Old school here, but bare metal programming since 6502, 68000 and later...

Regards,

Chris

[Chris Quayle]

Posted on July 21, 2017 at 23:07

Hi,

Thanks for the reply. See later reply to Vangelis to see what i'm asking...

Regards,

Chris

[Chris1]

Posted on July 21, 2017 at 23:14

You may have to look at ARM's CMSIS source (file core_cm3.h, widely available). I agree this information ought to exist in a proper document, but maybe it doesn't.

In core_cm3.h you can see various mask definitions and translations from IRQ number to register bits, fro example:

/**
* @brief Enable Interrupt in NVIC Interrupt Controller
*
* @param IRQn The positive number of the external interrupt to enable
*
* Enable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}

[Tesla DeLorean]

Posted on July 21, 2017 at 23:27

You're trying to over complicate this, they translate into a linear bit vector that spans multiple registers. A 32-bit register holds 32 bits, the LSB represents the lowest index. The NVIC->ISER[0] describes interrupt 0..31,

NVIC->ISER[1] describes .63, etc

The first 16 are system handlers/exceptions and are treated differently by the NVIC.

The WWDG is interrupt zero, so will be the first bit, of the first register described by

NVIC->ISER

[Tesla DeLorean]

Posted on July 21, 2017 at 23:41

>>

This is a serious gap in the documentation as far as I can see.

ARM doesn't define how many interrupts the vendor supplies to the NVIC, so it is basically a bit vector of unspecified length, each 32 interrupts adds another register and advances the offset.

The ISER can be 8 x 32 bits deep (256 bits, 240 used), the IP has 240 x 8 bits, I suspect the IC designers think this is relatively straight forward and obvious, and thus not warranting explanation in excruciating detail.

Joseph Yiu's books might have coverage of this.

[Chris Quayle]

Posted on July 22, 2017 at 01:25

Thanks for the link. Just downloaded that and seems very complete. St seem to have put a shedload of effort into this and far more than any other vendor so far. However much of it we use, there's planty to dig into from a learning pov...

Regards,

Chris