STM32F103 and TIM3 and DMA - how to?

[vaclav23]

Posted on October 13, 2011 at 13:58

Hello all,

I have linebuffer[256] and want to quickly send it to GPIOB15-8. In TIM2_IRQ, I enable DMA and TIM3 is used for DMA requests. I am trying following configuration:

   RCC->APB1ENR = RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM2EN ; // enable TIM2 and TIM3

   RCC->AHBENR = RCC_AHBENR_DMA1EN; // enable DMA1    // config of TIM3 - for DMA    TIM3->ARR = 5;    TIM3->PSC = 0;   // f=72MHz, ARR=5, PSC=0 => fpixclk = 12MHz    TIM3->SMCR = 0;    TIM3->DIER = TIM_DIER_UDE; // DMA request enable    TIM3->CR2 = 0;    TIM3->CR1 = TIM_CR1_URS | TIM_CR1_CEN;

   // config of DMA1 channel3 - TIM3_UP

   DMA1_Channel3->CCR = 0x00003090;    DMA1_Channel3->CNDTR = 0x100; // 255 bytes    DMA1_Channel3->CPAR = ((unsigned char)&(GPIOB->ODR))+1;    DMA1_Channel3->CMAR = (unsigned char ) linebuffer;    DMA1_Channel3->CCR = 0x00003091; I assume that each TIM3_UP causes copying of one byte from linebuffer[] to GPIOB15-8. When 256 bytes is transferred, DMA stops and waits for reconfiguration in TIM2_IRQ. I noticed that TIM3 has DCR and DMAR registers. But I don't know at all, what they are good for. They seem to me that they are not used in DMA controller but just to self-update. Can anybody help ? #dma-timer

[Tesla DeLorean]

Posted on October 13, 2011 at 16:51

Can anybody help ?

Probably, what are you offering? I'd avoid register level programming the part, and I suspect 12 MHz is going to get pretty close to saturating the bus. How does this burst of data get latched externally, or are you trying to dump data to a logic analyser, or a scope trace? Do you plan to clock externally using a TIM output? Wouldn't shoveling out via an external bus (FSMC) in a memory-to-memory DMA, or Memory-to-GPIO DMA be more effective than using the timer at all?