STM32F031 SPI NSS in slave mode to frame beginning and end of a transfer

[Gregory Holcomb]

I am using a STM32F031 as a SPI slave device in close proximity to some motors that can cause some noise. I believe what happens is occasionally the STM interprets noise as a SPI clock which shifts my data one or more bits off. In the event I have a partial byte transferred due to unintended clocks then what is best to recover.

Does the master raising the hardware NSS signal high transfer what ever data is in the shift register into the RX FIFO and flush the partial TX byte? Do I need to poll for a condition of NSS high while BSY is set and reset the SPI manually in software?

[waclawek.jan]

The RM does not specify slave SPI behaviour upon NSS going high amidst a partial frame, so whatever is the actual case, you shouldn't really rely on it.

Regardless of this, you really should go any length necessary to maintain integrity of the SPI clock. You then can add a packetization/checksumming/retry level to your communication as an additional security step.

JW

[S.Ma]

Disable the peripheral when not using it, reinit the peripheral only when needed.

Noise, EMI, glitch requires HW touch up for its reduction (EMC). If this is not enough, consider using LVDS differential pairs for your digital signals.