Posted on October 21, 2014 at 15:05I am using an STM32F030 MCU, implementing a slave SPI interface using DMA.
The application uses a hardware NSS signal during the SPI transfer.
The application can use 2 different SPI message lengths, say 16-bit and 64-bit. The end of the SPI message is marked by NSS going inactive.
Now I am facing a problem:
Since this is a slave SPI, the TXFIFO (or TX Data Register) must contain valid data
before starting the transmission, so the first bit is ready as soon as NSS goes active. So, after transmitting the 16th bit, the TX DR or TXFIFO must be fed with the next 16-bit word.
But...
the master now decides that this is a
short message, so it deasserts NSS. When the master will assert NSS again, it will expect the slave to transmit the first 16 bits again.
But my slave SPI already contains the 2nd 16-bit word in its TXFIFO.
How can I flush the SPI TXFIFO in order to feed it with the new 16-bit word?
I mentioned that I am using the DMA, but I think the problem would be the same even if I used IRQ.
Thanks for your help,
Mauro
#txfifo #spi #stm32f0
