Posted on February 08, 2014 at 14:54First thing to understand is that peripheral registers/latches don't act like memory.
There is one set of latches for the GPIO output, writing to ODR gets there relatively directly, writing via BSRR, etc does so via combinational logic to effect the set/reset behaviour against the current context. This doesn't alter the speed at which this can be done. And doing the single write is significantly quicker than a processor based read-modify-write, and is atomic.
