Posted on May 17, 2011 at 13:00Hello STMicroExperts,
yesterday I programmed some test applications to access external SRAM. I am using the STM3210E Evaluation Board. It is working fine.
But then we wondered, how it works:
The SRAM has 19 address lines (a0...a18), which makes 2^19=524288 addresses. The address lines are 1 by 1 connected to the address lines of the STM32F103ZET6 controller, i.e a0 to a0, a1 to a1...
The SRAM '512x16' has a 16bit data bus. This makes 1MByte memory (more exactly 1MebiByte). So I assume that the address lines are ''word'' (2Byte) addresses (or if you are talking about 32bit-words, ''half-words'').
1) Are my assumptions correct?
In the C-Code and in the dissambly I can see byte addresses.
2) Does the FSMC convert the byte addresses to word addresses?
In the disassembly I could see that different addressing modes are used for byte and (half-)word access, assuming to interact with the SRAM via the byte lane signals (high-byte, lo-byte write).
Then I was reading a word from an odd address, 0x6800001. The result was OK.
3) How does the FSMC handle these accesses (assumed that there are word addresses inbetween memory and controller)? Are two access cycles used?!
Regards,
Michael
