STM32107 Default Clock configuration

[orlcp440]

Posted on January 19, 2014 at 07:54

I am trying to figure out the default clock speeds (after reset) for the buses and the peripherals and system clock for the STM32107VC. I am reading the STM32107 Reference Manual RM0008 on page 123.

One thing I do not understand is that the RCC_CFGR register reset value is 0x00000000. That register contains the PLLMUL field. Which is used to setup the clocks on page 123. When I look at the description of PLLMUL it says that the value 0x0 is reserved.Bits 21:18 PLLMUL[3:0]: PLL multiplication factor000x: ReservedHow can this be? because the value of PLLMUL 0x000x at reset, I cannot figured out what PLLCLK is. Is this a typo or something? #stm32 #stm32 #stm32 #stm32

[Tesla DeLorean]

Posted on January 19, 2014 at 08:52

The PLL is not running, it' settings are thus inconsequential.

The chip starts running the ~8 MHz HSI clock, with the other buses running off that.

[orlcp440]

Posted on January 19, 2014 at 09:08

I see what you mean. However, what would happen if I only changed the SW register to have the PLL selected as system clock? The behavior would be undefined?

[Tesla DeLorean]

Posted on January 19, 2014 at 09:21

Given that it's a synchronous design, I'd imagine it would stop functioning.

If you set the PLL up with unrealistic settings based on the input clock, things would likely just malfunction in assorted ways, as there aren't checks-and-balances on doing the wrong thing. The clocks and PLL have expectations in terms of sequencing and setting, this is reflected in the code associated with SystemInit(), and within system_stm32f1xx.c There are other expectations within the design, that APB1 will not be faster than APB2, for example

[orlcp440]

Posted on January 19, 2014 at 09:42

Ok I understand what you are saying. I have one more question. The SysTick has the SysTick Control and Status Register. There is a bit field called CLKSOURCE.

CLKSOURCE 0 = external reference clock.1 = core clock.I believe when they say core clock they mean the FCLK Cortex free running clock. However, I do not know what they mean by ''External Reference Clock'' here. To make things even more confusing in page 123 of RM0008 they also talk about a signal that is divided by 8 (/8) that goes to the Cortex System timer.I guess my question is, where is the External Reference Clock in the block diagram of page 123? Also why the block diagram only shows one clock source going into the Cortex System Timer?

[Tesla DeLorean]

Posted on January 19, 2014 at 10:20

The Cortex design permits a different clock source, one that probably doesn't need to be synchronous with the core. ie some video source or other magic value.

The clock tree on the F4 design is perhaps clearer. HCLK (AHB) is a gated version of FCLK (SYSCLK), the external input for the SYSTICK is FCLK/8 A prescaled clock is useful as the SysTick counter is only 24-bit, the DIV8 would permit a 1 Hz SysTick from a 72 MHz source. /** @defgroup SysTick_clock_source   * @{   */ #define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)

[orlcp440]

Posted on January 19, 2014 at 10:41

Cool, I did not looked at the code so I couldn't tell what was what. Thank you very much for your help. Now, I can configure everything without confusions.