Hi all,
I am working on an STM32H755 project using external QSPI NOR Flash.
I intend to use the QSPI Flash in two different ways:
1. Memory-mapped mode for read-only resources (UI assets, fonts, images, etc.)
2. Indirect mode for file system operations (writing dynamic parameters)
RTOS: RT-Thread (preemptive, priority-based scheduler)
My current design is as follows:
- All dynamic parameters are read from QSPI Flash at boot and cached in RAM.
- During runtime, all parameter access is done from RAM only.
- QSPI indirect access (erase/write) is performed only by a dedicated file system thread.
- When a write is needed:
- The file system thread enters a critical section
- QSPI memory-mapped mode is disabled
- Flash write/erase is performed in indirect mode
- Memory-mapped mode is re-enabled
- The thread then exits the critical section and yields CPU
The idea is to prevent context switches while memory-mapped mode is disabled, so that no other thread can access QSPI via memory-mapped addresses during this window.
Additionally:
- I avoid accessing QSPI memory-mapped regions from ISRs.
- UI and other threads do not access QSPI while file system write is ongoing.
My question is:
Is this approach fundamentally safe on STM32H755?
Are there still risks due to CPU cache refill, prefetch or other factors that are not controlled by RTOS critical sections?
If this approach is unsafe, what is the recommended way to safely switch between QSPI memory-mapped and indirect modes under RTOS?
Any insights or best practices would be greatly appreciated.
Thanks!
