STM32 Dac strange behaviour...

gullik · ‎2014-01-02

Posted on January 02, 2014 at 16:26

Hello,

I have been trying some waveform generation using DAC + DMA. This works quite nicely, and I am now generating I + Q waveforms for a small SDR radio project. Just to see what cand be done, I have pushed up the rates. As rates goes up, output slewing reduces the amplitude. This is expected, but I am still able to generate a reasonable waveform at 200 khz.

However, going to this rate, output level only spans 2 V pp, with a measured VDD of 2.956 V . DAC 2 is centered at half VDD, and reaches within 0.5 V from either VDD or GND.

But DAC 1 is centered on 2 V, and it does reach VDD, but the negative part only reaches 1 V, so it seems like a DC component is introduced.

So, I enabled the output buffers. Now I get some more amplitude, but the signal looks like a triangular, so slewing rate is *worse* when enabling buffers. The unbuffered waveform is a fairly nice sine, (which is from the sinetable), and slewing without buffers just smooths the signal to within 3-5% of an ideal sine, BUT with a DC offset on one DAC. Does anyone have an idea what is happening here?

G

#dac-dma-buffer

gullik · ‎2014-01-02

Posted on January 02, 2014 at 16:39

And since I discovered this forum is for *many* boards, the one I am using is the STM32F4Discovery.

raptorhal2 · ‎2014-01-02

Posted on January 02, 2014 at 17:33

It's deja vu all over again.

PA4 and PA5 have dedicated board connections that are probably affecting the loading conditions. See Table 2 in the Discovery board users reference manual.

Cheers, Hal

gullik · ‎2014-01-02

Posted on January 02, 2014 at 17:52

Thanks Hal, how come I did not realise this...

I will check if I can remove unnecessary stuff. This is probably why one DAC has a level shift. However, it seems PA4/PA5 are the only choices here.

Do you have any idea why slewing is WORSE when buffering?

Well, anyway I seem to be clocking 2 times to fast, 120 khz should be max with 8 samples / sine.

raptorhal2 · ‎2014-01-02

Posted on January 02, 2014 at 19:42

Do you have any idea why slewing is WORSE when buffering?

The datasheet gives a settling time with I presume buffer on (based on the spec loading condition) but not with buffer off. With so much going on in the chip, I doubt they dedicate the real estate for high performance buffer amps. Try feeding the buffer off outputs to the plus inputs of external buffer amps.

Cheers, Hal

gullik · ‎2014-01-07

Posted on January 07, 2014 at 15:35

Thanks for help and hints,

Almost a success. A bit of careful surgery on the board, and I can now generate a reasonable GSM I/Q baseband at 4 samples/bit, and a betterlooking but reduced amplitude at 8 samples/bit. The latter looks like less than 3% distorsion, after the low pass action of the DAC slewing rate, but unfortunately not predictable amplitude. Also, the board generates the BB @ 270.854 Kbit/sec,rather than 270.8333,but I guess that could be adjusted with a trimmer on the crystal. Pretty good for $15.