STM32 ADC basics

[marko2]

Posted on July 09, 2014 at 18:25

Dear all,

I'm new in embedded systems, and I have a few simple questions regarding ADC on STM32F4xx.1. In the processor block diagram, I can see that ADCs (there are three of them) are connected to APB2 that has operating clock frequency of 84 MHz. Is this 84 MHz clock frequency exactly 84 MHz, or this clock frequency can deviate? If it deviates, is it possible for it to deviate during the processor runtime, or is it just due to the material imperfection - something like inherent deviation that varies from a processor unit to processor unit? Or the number of peripheral devices powered on also affects APB2 clock frequency?2. I can see in the processor datasheet in ADC characteristics table that maximum ADC clock frequency is 36 MHz, with typical clock frequency of 30 MHz. However, in peripheral library I have available only Div2, 4, 6, and 8 options, which means that if I choose Div2 the ADC clock frequency will be 42 MHz, and if I choose Div4 the ADC clock frequency will be 21 MHz. How can I set this 30 MHz clock frequency that is stated as typical value? I suppose that Div4 option will not do, but if I choose Div2 option (42 MHz) what will happen then? Will something like this mess with ADC causing it not to perform well? Also, if I set 42 MHz, ADC will try to operate at 36 MHz, right?3. In Dual regular ADC mode, two ADCs are scanning their corresponding sequence of inputs (channels), but they are synchronized. E.g. current and voltage measurements are connected to ADC1_CH0 and ADC2_CH4, and this conversion mode will ensure that these channels (single or multiple of them) are converted at the same time instance?4. Considering sample time and conversion terms - during sample-time-cycles the ADC is ''collecting'' the signal, and during the conversion-cycles the ADC is actually transforming voltage level to bits? Sample time can be configured (less sample time means higher consumption, this is the only difference?), and conversion time (in cycles) depends on the ADC resolution (less bits, faster the conversion is)? #adc

[Tesla DeLorean]

Posted on July 09, 2014 at 19:03

1) What does ''Exactly 84 MHz'' actually mean? Do you have an accuracy number in mind, and can that be quoted as a percentage, ppm, ppb, etc? I don't think man has created oscillators which are ''exactly'' the same, there always tends to be drift, and accumulating bias.

Oscillators are impacted by voltage, temperature, and aging, among other things. The internal RC (HSI) is impacted by internal voltage, temperature, and process variations. ST specs it somewhere, but it's pretty rough and variable, and has no real calibration/compensation. The PLL uses a clock generated by a VCO, and compared against an input clock. 2) A number of specifications are mutually exclusive, to hit all the numbers you might have to run the processor at sub-optimal speeds, or pick magic crystal values. Remember this is a general purpose micro, not a high precision ADC solution. 3) Like mechanical gears in a clock, synchronization will depend of selecting the correct parameters, and using common sample times, and scan lists between different ADC. You can also use common triggers across multiple ADC, but this might limit you to a small subset of possible sources. You can sample up to 3 sources at a common clock edge. 4) The sample time depends on the signal, and it's impedance. You are trying to charge a capacitor to the input voltage. If you are sampling multiple inputs consider how fast this going to be able to happen, especially when those voltages might be significantly different to each other.

[marko2]

Posted on July 10, 2014 at 15:09

clive1,

Thank you for these explanations!1. Please let me know if I got it right - CPU clock can be either internal RC oscillator (by default) or some external clock source. According to the datasheet, internal RC oscillator operates at 16 MHz, and this clock source is input to a PLL that can generate frequencies up to 168 MHz (the max clock frequency at AHB). Therefore PLL is used to generate frequencies for peripheral (e.g. AHB, APB) as well as for CPU (or CPU uses 16 MHz clock?), and the accuracy of this clock depends on accuracy of both, RC oscillator and the PLL, which depend on operating conditions (voltage, temperature etc.)? This VCO is in fact RC or this is another unit? I couldn't find any more detailed information on VCO in datasheet.2. What you're saying is basically that I cannot use Div2 (since it would give 42 MHz, and the ADC can operate at max 36 MHz), therefore I have to use Div4 (equivalent for 21 MHz). If I want to use exactly 30 MHz (which is typical ADC frequency from the datasheet), I would have to use some external clock source?3. I can trigger up to 3 sources - by sources you mean ADCs, not channels (i.e. inputs)? So I can trigger 3 ADCs to scan multiple channels, and they will do this conversion in sync?4. So during sample time, signal is ''collected'' (capacitor is charged), and after that conversion can take place since capacitor voltage is now stabilized?Thank you again for answers!Marko.

[jpeacock2399]

Posted on July 10, 2014 at 15:43

If you want the maximum ADC clock rate for an F4 you have to drop the clock rate from 168MHz to 120MHz.  That yields 30MHz with a /4 prescale.

The ADC needs a stable voltage before starting a conversion.  So you need some type of sample and hold mechanism, usually a capacitor, to hold the sample point while it is converted.   Jack Peacock