2020-11-05 02:52 AM
Hi,
We were planning to use ST32H750VB (LQFP100 Package) in our design. The critical interface in our design will be SDRAM ( planning x16 bit).
But while checking pin-multiplexing details for LQFP100 package, we observed that the D[0-15] and A[0-15] are multiplexed together for LQFP100 package! But in reference manual, that gave us a different impression that data/address are shared among other memory controllers like NOR flash.
2020-11-05 06:03 AM
2020-11-06 03:35 AM
Hi TDK,
Thanks for your response.
As suggested in the above link, we also have manually done the Pin multiplexing in a Spreadsheet. We assume that Address and data lines have been multiplexed for the LQFP-100 package (from FMC_D(0:15), which is indicated as FMC_DA(0:15) too).
As omeryaman concluded at the end of the link you have shared, it will be useful for us if we get any official confirmation from STM or from ST Employees on this.
BTW do you see same/any other concerns with 144-pin or 176-pin packages too ?
Thanks.