2024-01-08 07:19 AM
Hello everyone.
I'm interfacing my STM32F745IET6 (master) with an SPI device.
I'm using SPI1 interface running at 50 MHz, I was wondering if there's some "rule of thumb" to calculate time needed (in terms of clock cycles) to write n bits over the bus.
Thank you very much in advanced
Nick
2024-01-08 07:38 AM
Um, "1 bit per clock". ;)
2024-01-08 07:39 AM
Beyond the obvious one, no.
Generally that sets a ceiling, where the data is continuously available, and DMA is servicing the input/output stream demands.