SPI clock phase setting

[bnp979]

Posted on January 06, 2015 at 09:26

I am using STM32L152 part to talk to a digital accelerometer using SPI.

The SPI signal timing diagram for the accelerometer is illustrated in the attached figure. Looking at the diagram, it is clear that the spi clock polarity should be high (1). I'd like some help determining the spi clock phase. The data output by the L1 device is latched by the accelerometer in the second (rising) edge. So to honor the required setup time, I am thinking that the L1 device should send SPI data out at the first (falling) edge. But I am wondering if this would mess up the timing for SDI sampling, because bit D7 is not ready by the falling edge of clock for the eighth bit (immediately following A0). Any clarification is appreciated. -Ben

[bnp979]

Posted on January 06, 2015 at 19:44

I'll rephrase (simplify) my question.

Is it possible to latch SDO at the falling edge of the clock but sample the SDI at the rising edge of the clock for SPI communication with the STM32L1 devices?This is assuming my clock polarity is high.Thanks,Ben

[Tesla DeLorean]

Posted on January 06, 2015 at 20:00

Is there a reason you don't actually cite the data sheet for the accelerometer, or it's part number?

[Tamas Novak]

Posted on January 06, 2015 at 21:57

Based on the attached timing scheme of the accelerometer, you must simply set the MCU SPI clock suitable for the given  tSCLK, tM and tS.

Contiguous clock is generated by master, so SPI slave must be quick enough to be able to transmit after the end of the master transmit within one clock cycle. No need to give ''more time'' by tricking the sampling point to L->H or H->L edges.

[bnp979]

Posted on January 07, 2015 at 07:51

@clive: the accelerometer is ADXl375 from Analog.

http://www.analog.com/en/mems-sensors/mems-accelerometers/adxl375/products/product.html@novak: I initially followed the approach you suggested, which is to set the SPI clock phase and polarity to 1 (mode 3). That is when I saw that the LSB is sporadically wrongly flipping (showing up as 1 instead of 0 and vice versa). This is why I delved into the nitty gritties of the timing.Also, the current project was previously implemented using a PIC uC, which you could set SDO to be output at the falling edge and SDI to be sample in the middle of the clock cycle. And using this setting, the uC and the accelerometer happily talked to one another.To reiterate, the problem I am seeing is that clock phase of both 1 and 0 leads to timing issues:* if its set to '0' then SDI sampling happens too early (at the falling edge by when the accelerometer hasn't put the data out yet)* if its set to '1' then SDO is output too late as the accelerometer expects it to be ready t_setup time before hte rising edge 

[John F.]

Posted on January 07, 2015 at 09:36

The ADXL375 Data Sheet clearly states, ''The maxi-mum SPI clock speed is 5 MHz with 100 pF maximum loading. The timing scheme requires clock polarity (CPOL) = 1 and clock phase (CPHA) = 1.''

The microcontroller is capable of up to 16MHz SPI clock. Use CPOL = 1 and CPHA = 1 and try reducing the microcontroller's SPI clock rate. In any case, keep it below 5 MHz. The setup time is only 5ns. If this does not solve your problems, check that you have correctly configured both devices by reading the manuals - again.

[Tesla DeLorean]

Posted on January 07, 2015 at 15:54

Yeah, I understand the problem, I'm just trying to make sense of the timing diagram (number of bits in transaction), and neither of your threads on the topic stated the part#. Data really should get accepted on the falling edge of the clock, and it either has too many or too few clocks.

The STM32 SPI implementation is a bit restrictive, and has poor CS management. I'll take a look at the data sheet in a bit.