Simultaneous DMAs: Poor docs or restrictive hardware?

[stmburns]

Posted on October 19, 2012 at 18:51

The STM32L1xx reference manual has this text in the DMA section:

1. The 7 requests from the peripherals (TIMx[2,3,4,6,7], ADC1, SPI[1,2], I2Cx[1,2], USARTx[1,2,3]) and DAC Channelx[1,2] are simply logically ORed before entering the DMA, this means that only one request must be enabled at a time. Refer to

   Figure 25: DMA request mapping

   . 

Can someone help me understand what this means?  It sounds like it is saying that only a single peripheral can have DMA enabled at any one time.  That seems like a terrible restriction.  It makes more sense that only one peripheral that is directed to a particular DMA channel can be enabled at once.  And the figure cited shows 7 OR gates, 1 for each channel.  That makes more sense, but it is not what the text says!  Can someone confirm that the 'sensible' meaning is true?Thanks...

[Tesla DeLorean]

Posted on October 19, 2012 at 19:02

DMA1 has seven channels, each channel has up to 5 potential sources.

The combinations of peripherals that can connect together is finite. You can support DMA to all 3 USARTs, but not SPI1 and USART3, for example. Figure 35, Page 205, Sources for each channel Table 40, Page 206, One peripheral source from each column/channel

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00240193.pdf

[stmburns]

Posted on October 19, 2012 at 19:31

Thank you.  So to put it another way, all channels can operate simultaneously; it's just that you can only have one source per channel.  That is certainly the more reasonable way, although I would still suggest that the wording in that paragraph that I cited is poor.  Thanks for confirming what I hoped...