Simple question about setting ADC's analog watchdog thresholds on NUCLEO-STM32F746ZG

[SCutl.1]

The reference manual (link below) gives some details regarding setting the high and low voltage thresholds for the ADC's analog watchdog in the ADC_HTR and ADC_LTR registers. However, I can't find any details explaining how the values put into bits [11:0] in each register map to a voltage. I assume that setting all 12 bits in ADC_HTR would equate to the highest possible threshold voltage, but how do we know what that voltage is? And does setting all bits in ADC_LTR mean that the low threshold is as low as it can go? Or does clearing all 12 bits set it to the minimum?

Happy Thanksgiving!

Here's a link to the reference manual:

https://www.st.com/content/ccc/resource/technical/document/reference_manual/c5/cf/ef/52/c0/f1/4b/fa/DM00124865.pdf/files/DM00124865.pdf/jcr:content/translations/en.DM00124865.pdf

[Peter BENSCH · Accepted solution]

The ADC within the STM32 always refers to the voltage between VREF+ and VREF-, which are connected to VDD and GND in your NUCLEO.

While the setting of all bits corresponds exactly to this voltage (0xFFF / 0xFFF * Vdiff) and clearing them to zero (0x000 / 0xFFF * Vdiff).

When your question is answered, please close this topic by choosing Select as Best.

/Peter

[SCutl.1]

Thank you! And I assume Vdiff = VREF+ - VREF-?

[Peter BENSCH]

Yes, absolutely correct.