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SDRAM STM32F429 FMC SDRAM DELAY

jacekborko
Associate II
Posted on May 10, 2015 at 22:47

The original post was too long to process during our migration. Please click on the attachment to read the original post.
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6 REPLIES 6
jijo137
Associate II
Posted on October 22, 2015 at 10:55

Hi Doopler,

I am also facing similar issue with the SDRAM. I am using STM32427IG. I have configured my system clock to 16 Mhz. 

If you could solve the issue, Please tell me how it can be done

Thanks

waclawek.jan
Super User
Posted on October 22, 2015 at 12:16

Incorrect refresh rate? I don't use FMC with DRAMs but I'd be surprised if 16MHz clock would be enough.

JW
jijo137
Associate II
Posted on October 25, 2015 at 14:22

I have mentioned the SDRAM init code below.

void SDRAM_Init(void)

{

  FMC_SDRAMInitTypeDef        FMC_SDRAMInitStructure;

  FMC_SDRAMTimingInitTypeDef  FMC_SDRAMTimingInitStructure; 

  

  /* Enable FMC clock */

  //rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);

  RCC_AHB3PeriphClockCmd(RCC_AHB3ENR_FMCEN, ENABLE);

  

  /* FMC Configuration ---------------------------------------------------------*/

  /* FMC SDRAM Bank configuration */   

   /* TMRD: 2 Clock cycles */

  FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay =2;     

  /* TXSR: min=70ns 2x62ns (was 6x11.90ns) */

  FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay =1;

  /* TRAS: min=42ns 1x62ns (was 4x11.90ns) max=120k (ns) */

  FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime =1; 

  /* TRC:  min=63 2x62ns (was 6x11.90ns) */        

  FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay =1;     

  /* TWR:  2 Clock cycles */

  FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime =2;      

  /* TRP:  15ns => 1x62ns ( was 2x11.90ns ) */

  FMC_SDRAMTimingInitStructure.FMC_RPDelay =1;               

  /* TRCD: 15ns => 1x62ns (was 2x11.90ns) */

  FMC_SDRAMTimingInitStructure.FMC_RCDDelay =1; 

    /* FMC SDRAM control configuration */

  FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;

  /* Row addressing: [8..0] (was [7:0]) */

  FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_9b;

  /* Column addressing: [12..0] (was [11:0]) */

  FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_13b; 

  FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;

  FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;

  FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_2; 

  FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;

  FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2; 

  FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_Enable; 

  FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;

  FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;

 

  /* FMC SDRAM bank initialization */

  FMC_SDRAMInit(&FMC_SDRAMInitStructure); 

  

  /* FMC SDRAM device initialization sequence */

  SDRAM_InitSequence(); 

}

I have stored the data in address 0xD03AED64 is  0xD03AEE2C. I could read correctly when I tried continously. However, when I tried to read the data after some time I am getting the value  0x903AED64.  My SDRAM  is Micron MT48LC16M16A2. It works fine even in 8 Mhz frequency.

Thanks,

Gigo

waclawek.jan
Super User
Posted on October 25, 2015 at 18:33

> My SDRAM  is Micron MT48LC16M16A2.

So what is its refresh period, and what is your refresh setting?

JW

jijo137
Associate II
Posted on October 26, 2015 at 08:29

The FMC clock is configured as half of SDCLK. ie. 8 Mhz (16mhz/2).  So, an instruction takes 125 ns (1/8 Mhz) time. I have set the refresh rate to 125 ns. In the code snippet of previous post, it is given FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime =1; So, I hope it is suppose to refresh the storage at every 125 nano seconds.

  When I have test the  fmc clock with 16 Mhz, this is working fine. But when I reduced the fmc clock to 8 Mhz, I am getting this error

waclawek.jan
Super User
Posted on October 26, 2015 at 11:23

I suggest you to read thoroughly the SDRAM sub-chapter of the FMC chapter in RM and the memory's datasheet, concentrating on the refresh issues.

JW