SCB_VTOR description incorrect in PM0056 and bug in misc.c:NVIC_SetVectorTable

[hazelnusse]

Posted on September 08, 2011 at 02:00

In section 4.4.4, page 134, of  the STM32 Cortex-M3 programming manual (PM0056, Rev 4), the vector table offset register is shown as being partitioned in three sections:

[31:30]  -- reserved[29:9] -- TBLOFF[8:0] -- reservedIn the description, however, TBLOFF is described as occupying bits [29:11], and bits [10:0] are said to be reserved.   According to the description, the table must have a minimum alignment of 128 words (4 bytes / word *  128 words = 512 bytes), so having bits [8:0] as reserved makes sense (2 ^ 9 = 512).It seems contradictory that in the bit field picture, bits 9 and 10 are marked as ''rw'', but in the bit description below this picture, it is stated that bits 10:0 are reserved and must be kept clear.It seems that the bit field picture is likely correct, but that the bit descriptions should read:Bits 31:30 ...Bits 29:9  ...Bits 8:0  ...instead of:Bits 31:30 ...Bits 29:11  ...Bits 10:0  ..In looking at the part of the firmware library that manipulates this register (misc.h/misc.c, function NVIC_SetVectorTable), we have the following:misc.h:#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)misc.c:void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset){  ...  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);}In particular, this part seems incorrect:(Offset & (uint32_t)0x1FFFFF80)This clears bits [31:29] and bits [6:0] of Offset, which is presumably being done to clear all the bits in the reserved parts of the SCB_VTOR register.  The clearing of bits [31:29] seems reasonable given that the result will be bitwise or'd with either NVIC_VectTab_RAM or NVIC_VecTab_Flash.  However, clearing bits[6:0] doesn't seem correct.  Instead it seems (assuming my preceding arguments about PM0056 above are correct) that bits [8:0] should be cleared, so the correct code would read:SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFE00);If I am correct, this means there is a typo in PM0056, as well as a bug in NVIC_SetVectorTable of misc.c in the STM32 standard peripheral library.Can anybody confirm this?

[Tesla DeLorean]

Posted on September 08, 2011 at 02:57

The function presupposes you don't specify stupid values, it doesn't generate any errors, so if you pass it a value that doesn't fit, you and the CPU still have different ideas about where the table is situated.

Personally, I just use the first parameter, and explicitly pass the exact address of the table, and the value I want in the register. The STM32 family has quite a range of different interrupts, depending on the peripheral set. (0x120-0x1E0). The Cortex-M3 VTOR register is implementation specific, pretty sure it needs to be on a 512 (0x200) byte boundary on the STM32F1

[hazelnusse]

Posted on September 09, 2011 at 00:03

So, ARM Cortex-M3 spec declares that bits[6:0] must be reserved (i.e., the vector table must be at minimum 32 word aligned).  This is what the ST Standard Peripheral library implements -- it masks off bits [6:0] of the offset you pass.

However, the data sheet is still contradictory.  In two places of PM0056 (page 134 in the bit field diagram, and page 148) it is shown that bits [8:0] are reserved.  However, the last line of page 134 says Bits 10:0 are reserved, and this is wrong.